An FPGA Connect6 Solver with a two-stage pipelined evaluation. - Takahiro Watanabe; Retsu Moriwaki; Yuichiro Yamaji; Yuki Kamikubo; Yuki Torigai; Yuki Nihira; Takashi Yoza; Yumiko Ueno; Yuji Aoyama; Minoru Watanabe (FPT, 2011)

Triple module redundancy scheme on an optically reconfigure gate array. - Yuki Torigai; Minoru Watanabe (ISOCC, 2011)

FPGA Blokus Duo Solver using a massively parallel architecture. - Takashi Yoza; Retsu Moriwaki; Yuki Torigai; Yuki Kamikubo; Takayuki Kubota; Takahiro Watanabe; Takumi Fujimori; Hiroyuki Ito; Masato Seo; Kouta Akagi; Yuichiro Yamaji; Minoru Watanabe (FPT, 2013)