Maximum PLA folding using inverters. - Yukihiro Iguchi; Masao Mukaidono (Syst. Comput. Jpn., 1989)

On properties of Kleene TDDs. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (ASP-DAC, 1997)

On Decomposition of Kleene TDDs. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (Asian Test Symposium, 1997)

Realization of Regular Ternary Logic Functions. - Yukihiro Iguchi; Munehiro Matsuura; Tsutomu Sasao; Atsumu Iseno (ASP-DAC, 1999)

A hardware simulation engine based on decision diagrams (short paper). - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura; Atsumu Iseno (ASP-DAC, 2000)

Implementation of Multiple-Output Functions Using PQMDDs. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (ISMVL, 2000)

Realization of Multiple-Output Functions by Reconfigurable Cascades. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (ICCD, 2001)

A Method for Storing Fail Bit Maps in Burn-in Memory Testers. - Atsumu Iseno; Yukihiro Iguchi (DELTA, 2002)

Representations of Logic Functions Using QRMDDs. - Shinobu Nagayama; Tsutomu Sasao; Yukihiro Iguchi; Munehiro Matsuura (ISMVL, 2002)

Comparison of Decision Diagrams for Multiple-Output Logic Functions. - Tsutomu Sasao; Yukihiro Iguchi; Munehiro Matsuura (IWLS, 2002)

Bi-Partition of Shared Binary Decision Diagrams. - Munehiro Matsuura; Tsutomu Sasao; Jon T. Butler; Yukihiro Iguchi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Evaluation of multiple-output logic functions using decision diagrams. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (ASP-DAC, 2003)

A Method to Evaluate Logic Functions in the Presence of Unknown Inputs Using LUT Cascades. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (ISMVL, 2004)

Fault Diagnosis for RAMs Using Walsh Spectrum. - Atsumu Iseno; Yukihiro Iguchi; Tsutomu Sasao (IEICE Trans. Inf. Syst., 2004)

On LUT Cascade Realizations of FIR Filters. - Tsutomu Sasao; Yukihiro Iguchi; Takahiro Suzuki (DSD, 2005)

An FPGA design of AES encryption circuit with 128-bit keys. - Hui Qin; Tsutomu Sasao; Yukihiro Iguchi (ACM Great Lakes Symposium on VLSI, 2005)

Hardware to Compute Walsh Coefficients. - Yukihiro Iguchi; Tsutomu Sasao (ISMVL, 2005)

On Designs of Radix Converters Using Arithmetic Decompositions. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (ISMVL, 2006)

A Design of AES Encryption Circuit with 128-bit Keys Using Look-Up Table Ring on FPGA. - Hui Qin; Tsutomu Sasao; Yukihiro Iguchi (IEICE Trans. Inf. Syst., 2006)

On Designs of Radix Converters Using Arithmetic Decompositions–Binary to Decimal Converters–. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (ISMVL, 2007)

Design Methods of Radix Converters Using Arithmetic Decompositions. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (IEICE Trans. Inf. Syst., 2007)

Design Methods for Binary to Decimal Converters Using Arithmetic Decompositions. - Yukihiro Iguchi; Tsutomu Sasao; Munehiro Matsuura (J. Multiple Valued Log. Soft Comput., 2007)

On the Complexity of Error Detection Functions for Redundant Residue Number Systems. - Tsutomu Sasao; Yukihiro Iguchi (DSD, 2008)

A Realization Method of Forward Converters from Multiple-Precision Binary Numbers to Residue Numbers with Arbitrary Mutable Modulus. - Koki Shirakawa; Takashi Uemura; Yukihiro Iguchi (ISMVL, 2011)

A Lower Bound on the Number of Variables to Represent Incompletely Specified Index Generation Functions. - Tsutomu Sasao; Yuta Urano; Yukihiro Iguchi (ISMVL, 2014)

A Method to Find Linear Decompositions for Incompletely Specified Index Generation Functions Using Difference Matrix. - Tsutomu Sasao; Yuta Urano; Yukihiro Iguchi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

An algorithm to find optimum support-reducing decompositions for index generation functions. - Tsutomu Sasao; Kyu Matsuura; Yukihiro Iguchi (DATE, 2017)

Handwritten Digit Recognition Based on Classification Functions. - Tsutomu Sasao; Yuto Horikawa; Yukihiro Iguchi (ISMVL, 2020)

A Design Method for Multiclass Classifiers. - Tsutomu Sasao; Yuto Horikawa; Yukihiro Iguchi (ISMVL, 2021)

Classification Functions for Handwritten Digit Recognition. - Tsutomu Sasao; Yuto Horikawa; Yukihiro Iguchi (IEICE Trans. Inf. Syst., 2021)