An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode. - Shigeyoshi Watanabe; Yukihito Oowaki; Yasuo Itoh; Koji Sakui; Kenji Numata; Tsuneaki Fuse; Takayuki Kobayashi; Kenji Tsuchida; Masahiko Chiba; Takahiko Hara; Masako Ohta; Fumio Horiguchi; et al. (IEEE J. Solid State Circuits, 1989)

New nibbled-page architecture for high-density DRAMs. - Kenji Numata; Yukihito Oowaki; Yasuo Itoh; Takahiko Hara; Kenji Tsuchida; Masako Ohta; Shigyoshi Watanabe; Kazunori Ohuchi (IEEE J. Solid State Circuits, 1989)

The stabilized reference-line (SRL) technique for scaled DRAMs. - Kenji Tsuchida; Yukihito Oowaki; Masako Ohta; Daisaburo Takashima; Shigeyoshi Watanabe; Kazuya Ohuchi; Fujio Masuoka (IEEE J. Solid State Circuits, 1990)

A 33-ns 64-Mb DRAM. - Yukihito Oowaki; Kenji Tsuchida; Yohji Watanabe; Daisaburo Takashima; Masako Ohta; Hiroaki Nakano; Shigeyoshi Watanabe; Akihiro Nitayama; Fumio Horiguchi; Kazunori Ohuchi; Fujio Masuoka (IEEE J. Solid State Circuits, 1991)

Word-line architecture for highly reliable 64-Mb DRAM. - Daisaburo Takashima; Yukihito Oowaki; Ryu Ogiwara; Yohji Watanabe; Kenji Tsuchida; Masako Ohta; Hiroaki Nakano; Shigeyoshi Watanabe; Kazunori Ohuchi (IEEE J. Solid State Circuits, 1992)

An experimental DRAM with a NAND-structured cell. - Takehiro Hasegawa; Daisaburo Takashima; Ryu Ogiwara; Masako Ohta; Shinichiro Shiratake; Takeshi Hamamoto; Takashi Yamada; Masami Aoki; Shigeru Ishibashi; Yukihito Oowaki; Shigeyoshi Watanabe; Fujio Masuoka (IEEE J. Solid State Circuits, 1993)

Open/folded bit-line arrangement for ultra-high-density DRAM's. - Daisaburo Takashima; Shigeyoshi Watanabe; Hiroaki Nakano; Yukihito Oowaki; Kazunori Ohuchi (IEEE J. Solid State Circuits, 1994)

Standby/active mode logic for sub-1-V operating ULSI memory. - Daisaburo Takashima; Shigeyoshi Watanabe; Hiroalu Nakano; Yukihito Oowaki; Kazunori Ohuchi; Hiroyuki Tango (IEEE J. Solid State Circuits, 1994)

A novel power-off mode for a battery-backup DRAM. - Daisaburo Takashima; Yukihito Oowaki (IEEE J. Solid State Circuits, 1997)

Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI's. - Daisaburo Takashima; Yukihito Oowaki; Shigeyoshi Watanabe; Kazunori Ohuchi (IEEE J. Solid State Circuits, 1998)

A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive. - Daisaburo Takashima; Susumu Shuto; Iwao Kunishima; Hiroyuki Takenaka; Yukihito Oowaki; Shin'ichi Tanaka (IEEE J. Solid State Circuits, 1999)

A 76-mm2 8-Mb chain ferroelectric memory. - Daisaburo Takashima; Yoshiaki Takeuchi; Tadashi Miyakawa; Yasuo Itoh; Ryu Ogiwara; Masahiro Kamoshida; Katsuhiko Hoya; Sumiko Mano Doumae; Tohru Ozaki; Hiroyuki Kanaya; Koji Yamakawa; Iwao Kunishima; et al. (IEEE J. Solid State Circuits, 2001)

A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI. - Mototsugu Hamada; Hiroyuki Hara; Tetsuya Fujita; Chen Kong Teh; Takayoshi Shimazawa; Naoyuki Kawabe; Takeshi Kitahara; Yu Kikuchi; Tsuyoshi Nishikawa; Makoto Takahashi; Yukihito Oowaki (CICC, 2005)

Module-Wise Dynamic Voltage and Frequency Scaling for a 90 nm H.264/MPEG-4 Codec LSI. - Yukihito Oowaki; Shinichiro Shiratake; Toshihide Fujiyoshi; Mototsugu Hamada; Fumitoshi Hatori; Masami Murakata; Masafumi Takahashi (IEICE Trans. Electron., 2006)

A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling. - Toshihide Fujiyoshi; Shinichiro Shiratake; Shuou Nomura; Tsuyoshi Nishikawa; Yoshiyuki Kitasho; Hideho Arakida; Yuji Okuda; Yoshiro Tsuboi; Mototsugu Hamada; Hiroyuki Hara; Tetsuya Fujita; Fumitoshi Hatori; et al. (IEEE J. Solid State Circuits, 2006)

Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems. - Chen Kong Teh; Mototsugu Hamada; Tetsuya Fujita; Hiroyuki Hara; N. Ikumi; Yukihito Oowaki (IEEE Trans. Very Large Scale Integr. Syst., 2006)

An automated runtime power-gating scheme. - Mototsugu Hamada; Takeshi Kitahara; Naoyuki Kawabe; Hironori Sato; Tsuyoshi Nishikawa; Takayoshi Shimazawa; Takahiro Yamashita; Hiroyuki Hara; Yukihito Oowaki (ICCD, 2007)

A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm. - Yu Kikuchi; Makoto Takahashi; Tomohisa Maeda; Hiroyuki Hara; Hideho Arakida; Hideaki Yamamoto; Yousuke Hagiwara; Tetsuya Fujita; Manabu Watanabe; Takayoshi Shimazawa; Yasuo Ohara; Takashi Miyamori; et al. (ISSCC, 2010)

Development of low power and high performance application processor (T6G) for multimedia mobile applications. - Yoshiyuki Kitasho; Yu Kikuchi; Takayoshi Shimazawa; Yasuo Ohara; Masafumi Takahashi; Yoshio Masubuchi; Yukihito Oowaki (ASP-DAC, 2011)

A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM. - Yu Kikuchi; Makoto Takahashi; Tomohisa Maeda; Masatoshi Fukuda; Yasuhiro Koshio; Hiroyuki Hara; Hideho Arakida; Hideaki Yamamoto; Yousuke Hagiwara; Tetsuya Fujita; Manabu Watanabe; Hirokazu Ezawa; et al. (IEEE J. Solid State Circuits, 2011)

A 10.4pJ/b (32, 8) LDPC decoder with time-domain analog and digital mixed-signal processing. - Daisuke Miyashita; Ryo Yamaki; Kazunori Hashiyoshi; Hiroyuki Kobayashi; Shouhei Kousai; Yukihito Oowaki; Yasuo Unekawa (ISSCC, 2013)

A UHS-II SD card controller with 240MB/s write throughput and 260MB/s read throughput. - Kenta Yasufuku; Naoto Oshiyama; Toshitada Saito; Yukimasa Miyamoto; Yutaka Nakamura; Ryota Terauchi; Atsushi Kondo; Takuma Aoyama; Masafumi Takahashi; Yukihito Oowaki; Ryoichi Bandai (A-SSCC, 2014)

19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension. - Konosuke Watanabe; Kenichiro Yoshii; Nobuhiro Kondo; Ken-ichi Maeda; Toshio Fujisawa; Junji Wadatsumi; Daisuke Miyashita; Shouhei Kousai; Yasuo Unekawa; Shinsuke Fujii; Takuma Aoyama; Takayuki Tamura; et al. (ISSCC, 2014)

An LDPC Decoder With Time-Domain Analog and Digital Mixed-Signal Processing. - Daisuke Miyashita; Ryo Yamaki; Kazunori Hashiyoshi; Hiroyuki Kobayashi; Shouhei Kousai; Yukihito Oowaki; Yasuo Unekawa (IEEE J. Solid State Circuits, 2014)

Caching mechanisms towards single-level storage systems for Internet of Things. - Yosuke Bando; Konosuke Watanabe; Ken-ichi Maeda; Hiroki Kudo; Masahiro Ishiyama; Atsushi Kunimatsu; Hiroto Nakai; Masafumi Takahashi; Yukihito Oowaki (VLSIC, 2015)