Self-reforming routing for stochastic search in VLSI interconnection layout. - Yukiko Kubo; Yasuhiro Takashima; Shigetoshi Nakatake; Yoji Kajitani (ASP-DAC, 2000)

Consistent floorplanning with super hierarchical constraints. - Shigetoshi Nakatake; Yukiko Kubo; Yoji Kajitani (ISPD, 2001)

Chip size estimation based on wiring area. - Yukiko Kubo; Shigetoshi Nakatake; Yoji Kajitani; Masahiro Kawakita (APCCAS (2), 2002)

Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts. - Yukiko Kubo; Shigetoshi Nakatake; Yoji Kajitani; Masahiro Kawakita (ASP-DAC/VLSI Design, 2002)

Consistent floorplanning with hierarchical superconstraints. - Shigetoshi Nakatake; Yukiko Kubo; Yoji Kajitani (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

An Incremental Wiring Algorithm for VLSI Layout Design. - Yukiko Kubo; Shigetoshi Nakatake; Yoji Kajitani; Masahiro Kawakita (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

A global routing method for 2-layer ball grid array packages. - Yukiko Kubo; Atsushi Takahashi 001 (ISPD, 2005)

A Via Assignment and Global Routing Method for 2-Layer Ball Grid Array Packages. - Yukiko Kubo; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Equidistance routing in high-speed VLSI layout design. - Yukiko Kubo; Hiroshi Miyashita; Yoji Kajitani; Kazuyuki Tateishi (Integr., 2005)

Global Routing by Iterative Improvements for Two-Layer Ball Grid Array Packages. - Yukiko Kubo; Atsushi Takahashi 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)