An 8-bit 2-ns monolithic DAC. - Tsutomu Kamoto; Yukio Akazawa; Mitsuru Shinagawa (IEEE J. Solid State Circuits, 1988)

Si bipolar 2-GHz 6-bit flash A/D conversion LSI. - Tsutomu Wakimoto; Yukio Akazawa; Shinsuke Konaka (IEEE J. Solid State Circuits, 1988)

Jitter analysis of high-speed sampling systems. - Mitsuru Shinagawa; Yukio Akazawa; Tsutomu Wakimoto (IEEE J. Solid State Circuits, 1990)

A low-power wide-band amplifier using a new parasitic capacitance compensation technique. - Tsutomu Wakimoto; Yukio Akazawa (IEEE J. Solid State Circuits, 1990)

Circuits to reduce distortion in the diode-bridge track-and-hold. - Tsutomu Wakimoto; Yukio Akazawa (IEEE J. Solid State Circuits, 1993)

A monolithic 156 Mb/s clock and data recovery PLL circuit using the sample-and-hold technique. - Noboru Ishihara; Yukio Akazawa (IEEE J. Solid State Circuits, 1994)

A design technique for a 60 GHz-bandwidth distributed baseband amplifier IC module. - Tsugumichi Shibata; Shunji Kimura; Hideaki Kimura 002; Yuhki Imai; Yohtaro Umeda; Yukio Akazawa (IEEE J. Solid State Circuits, 1994)

3.5-Gb/s⨉4-ch Si bipolar LSI's for optical interconnections. - Noboru Ishihara; Shuichi Fujita; Minoru Togashi; Shigeki Hino; Yoshimitsu Arai; Nobuyuki Tanaka; Yoshiji Kobayashi; Yukio Akazawa (IEEE J. Solid State Circuits, 1995)

A 156-Mb/s CMOS optical receiver for burst-mode transmission. - Makoto Nakamura; Noboru Ishihara; Yukio Akazawa (IEEE J. Solid State Circuits, 1998)