A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond. - Yoshihide Komatsu; Yukio Arima; Tetsuya Fujimoto; Takahiro Yamashita; Koichiro Ishibashi (CICC, 2004)

A Spread Spectrum Clock Generator Using Digital Tracking Scheme. - Takefumi Yoshikawa; Tsuyoshi Ebuchi; Yukio Arima; Toru Iwata (IEICE Trans. Electron., 2005)

Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond. - Koichiro Ishibashi; Tetsuya Fujimoto; Takahiro Yamashita; Hiroyuki Okada; Yukio Arima; Yasuyuki Hashimoto; Kohji Sakata; Isao Minematsu; Yasuo Itoh; Haruki Toda; Motoi Ichihashi; Yoshihide Komatsu; et al. (IEICE Trans. Electron., 2006)

Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond. - Yoshihide Komatsu; Yukio Arima; Koichiro Ishibashi (IEICE Trans. Electron., 2006)

An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics. - Takefumi Yoshikawa; Takashi Hirata; Tsuyoshi Ebuchi; Toru Iwata; Yukio Arima; Hiroyuki Yamauchi (IEEE Trans. Very Large Scale Integr. Syst., 2008)

A 125-1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration. - Tsuyoshi Ebuchi; Yoshihide Komatsu; Tatsuo Okamoto; Yukio Arima; Yuji Yamada; Kazuaki Sogawa; Kouji Okamoto; Takashi Morie; Takashi Hirata; Shiro Dosho; Takefumi Yoshikawa (IEEE J. Solid State Circuits, 2009)