250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture. - Yasuhiro Takai; Mamoru Nagase; Mamoru Kitamura; Yasuji Koshikawa; Naoyuki Yoshida; Yasuaki Kobayashi; Takashi Obara; Yukio Fukuzo; Hiroshi Watanabe (IEEE J. Solid State Circuits, 1994)

A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay. - Takanori Saeki; Yuji Nakaoka; Mamoru Fujita; Akihito Tanaka; Kyoichi Nagata; Kenichi Sakakibara; Tatsuya Matano; Yukio Hoshino; Kazutaka Miyano; Satoshi Isa; Shigeyuki Nakazawa; Eiichiro Kakehashi; et al. (IEEE J. Solid State Circuits, 1996)