A 5-MHz, 3.6-mW, 1.4-V SRAM with nonboosted, vertical bipolar bit-line contact memory cell. - Hirotoshi Sato; Hideaki Nagaoka; Hiroaki Honda; Yukio Maki; Tomohisa Wada; Yutaka Arita; Kazuhito Tsutsumi; Makoto Taniguchi; Michihiro Yamada (IEEE J. Solid State Circuits, 1998)

A 500-MHz pipelined burst SRAM with improved SER immunity. - Hirotoshi Sato; Tomohisa Wada; Shigeki Ohbayashi; Kunihiko Kozaru; Yasuyuki Okamoto; Yoshiko Higashide; Tadayuki Shimizu; Yukio Maki; Rui Morimoto; Hisakazu Otoi; Tsuyoshi Koga; Hiroki Honda; et al. (IEEE J. Solid State Circuits, 1999)

A 0.05?0.05mm2 RFID Chip with Easily Scaled-Down ID-Memory. - Mitsuo Usami; Hisao Tanabe; Akira Sato; Isao Sakama; Yukio Maki; Toshiaki Iwamatsu; Takashi Ipposhi; Yasuo Inoue (ISSCC, 2007)