FeRAM Circuit Technology for System on a Chip. - Koji Asari; Yukio Mitsuyama; Takao Onoye; Isao Shirakawa; Hiroshige Hirano; Toshiyuki Honda; Tatsuo Otsuki; Takaaki Baba; Teresa H. Meng (Evolvable Hardware, 1999)

A dynamically reconfigurable hardware-based cipher chip. - Yukio Mitsuyama; Zaldy Andales; Takao Onoye; Isao Shirakawa (ASP-DAC, 2001)

VLSI architecture of dynamically reconfigurable hardware-based cipher. - Yukio Mitsuyama; Zaldy Andales; Takao Onoye; Isao Shirakawa (ISCAS (4), 2001)

Burst mode: a new acceleration mode for 128-bit block ciphers. - Yukio Mitsuyama; Zaldy Andales; Takao Onoye; Isao Shirakawa (CICC, 2002)

Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems. - Yukio Mitsuyama; Motoki Kimura; Takao Onoye; Isao Shirakawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Experimental study on body-biasing layout style– negligible area overhead enables sufficient speed controllability –. - Koichi Hamamoto; Hiroshi Fuketa; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye (ACM Great Lakes Symposium on VLSI, 2008)

Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits. - Hiroshi Fuketa; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye (ISLPED, 2008)

Area-Efficient Reconfigurable Architecture for Media Processing. - Yukio Mitsuyama; Kazuma Takahashi; Rintaro Imai; Masanori Hashimoto; Takao Onoye; Isao Shirakawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits. - Hiroshi Fuketa; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye (CICC, 2009)

Coarse-grained dynamically reconfigurable architecture with flexible reliability. - Dawood Alnajiar; Younghun Ko; Takashi Imagawa; Hiroaki Konoura; Masayuki Hiromoto; Yukio Mitsuyama; Masanori Hashimoto; Hiroyuki Ochi; Takao Onoye (FPL, 2009)

Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits. - Koichi Hamamoto; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye (ISLPED, 2009)

Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction. - Hiroshi Fuketa; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability. - Koichi Hamamoto; Hiroshi Fuketa; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye (IEICE Trans. Electron., 2009)

Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits. - Hiroshi Fuketa; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye (ASP-DAC, 2010)

Measurement circuits for acquiring SET pulsewidth distribution with sub-FO1-inverter-delay resolution. - Ryo Harada; Yukio Mitsuyama; Masanori Hashimoto; Takao Onoye (ISQED, 2010)

Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration. - Hiroaki Konoura; Yukio Mitsuyama; Masanori Hashimoto; Takao Onoye (ISQED, 2010)

A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling. - Takehiko Amaki; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye (WISA, 2010)

Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution. - Ryo Harada; Yukio Mitsuyama; Masanori Hashimoto; Takao Onoye (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits. - Hiroshi Fuketa; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures. - Hiroaki Konoura; Yukio Mitsuyama; Masanori Hashimoto; Takao Onoye (FPL, 2011)

NBTI Mitigation by Giving Random Scan-in Vectors during Standby Mode. - Toshihiro Kameda; Hiroaki Konoura; Yukio Mitsuyama; Masanori Hashimoto; Takao Onoye (PATMOS, 2011)

Stress Probability Computation for Estimating NBTI-Induced Delay Degradation. - Hiroaki Konoura; Yukio Mitsuyama; Masanori Hashimoto; Takao Onoye (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

A predictive delay fault avoidance scheme for coarse-grained reconfigurable architecture. - Toshihiro Kameda; Hiroaki Konoura; Dawood Alnajiar; Yukio Mitsuyama; Masanori Hashimoto; Takao Onoye (FPL, 2012)

Static voltage over-scaling and dynamic voltage variation tolerance with replica circuits and time redundancy in reconfigurable devices. - Dawood Alnajiar; Masanori Hashimoto; Takao Onoye; Yukio Mitsuyama (ReConFig, 2012)

Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits. - Hiroshi Fuketa; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design. - Hiroaki Konoura; Dawood Alnajiar; Yukio Mitsuyama; Hiroyuki Ochi; Takashi Imagawa; Shinichi Noda; Kazutoshi Wakabayashi; Masanori Hashimoto; Takao Onoye (ReConFig, 2013)

PVT-induced timing error detection through replica circuits and time redundancy in reconfigurable devices. - Dawood Alnajiar; Yukio Mitsuyama; Masanori Hashimoto; Takao Onoye (IEICE Electron. Express, 2013)

Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices. - Toshihiro Kameda; Hiroaki Konoura; Dawood Alnajiar; Yukio Mitsuyama; Masanori Hashimoto; Takao Onoye (IEICE Trans. Inf. Syst., 2013)

A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator With Stochastic Behavior Modeling. - Takehiko Amaki; Masanori Hashimoto; Yukio Mitsuyama; Takao Onoye (IEEE Trans. Inf. Forensics Secur., 2013)

Implementing Flexible Reliability in a Coarse-Grained Reconfigurable Architecture. - Dawood Alnajiar; Hiroaki Konoura; Younghun Ko; Yukio Mitsuyama; Masanori Hashimoto; Takao Onoye (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Variability and Soft-Error Resilience in Dependable VLSI Platform. - Yukio Mitsuyama; Hidetoshi Onodera (ATS, 2014)

SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects. - Ryo Harada; Yukio Mitsuyama; Masanori Hashimoto; Takao Onoye (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing. - Hiroaki Konoura; Dawood Alnajiar; Yukio Mitsuyama; Hajime Shimada; Kazutoshi Kobayashi; Hiroyuki Kanbara; Hiroyuki Ochi; Takashi Imagawa; Kazutoshi Wakabayashi; Masanori Hashimoto; Takao Onoye; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices. - Hiroaki Konoura; Takashi Imagawa; Yukio Mitsuyama; Masanori Hashimoto; Takao Onoye (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time. - Hiroaki Konoura; Toshihiro Kameda; Yukio Mitsuyama; Masanori Hashimoto; Takao Onoye (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis. - Masanori Hashimoto; Dawood Alnajiar; Hiroaki Konoura; Yukio Mitsuyama; Hajime Shimada; Kazutoshi Kobayashi; Hiroyuki Kanbara; Hiroyuki Ochi; Takashi Imagawa; Kazutoshi Wakabayashi; Takao Onoye; Hidetoshi Onodera (ASP-DAC, 2015)

A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch. - Junshi Hotate; Takashi Kishimoto; Toshiki Higashi; Hiroyuki Ochi; Ryutaro Doi; Munehiro Tada; Tadahiko Sugibayashi; Kazutoshi Wakabayashi; Hidetoshi Onodera; Yukio Mitsuyama; Masanori Hashimoto (FPL, 2016)

Design Flow and Design Tools. - Tomonori Izumi; Yukio Mitsuyama (Principles and Structures of FPGAs, 2018)

Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture. - Hiroki Hihara; Akira Iwasaki; Masanori Hashimoto; Hiroyuki Ochi; Yukio Mitsuyama; Hidetoshi Onodera; Hiroyuki Kanbara; Kazutoshi Wakabayashi; Tadahiko Sugibayashi; Takashi Takenaka; Hiromitsu Hada; Munehiro Tada; et al. (IEEE Embed. Syst. Lett., 2018)

Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars. - Hiroyuki Ochi; Kosei Yamaguchi; Tetsuaki Fujimoto; Junshi Hotate; Takashi Kishimoto; Toshiki Higashi; Takashi Imagawa; Ryutaro Doi; Munehiro Tada; Tadahiko Sugibayashi; Wataru Takahashi 002; Kazutoshi Wakabayashi; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Development of Autonomous Driving System Using Programmable SoCs. - Tomonari Tanaka; Itsuki Ikeno; Riku Tsuruoka; Takumi Kuchiba; Wang Liao; Yukio Mitsuyama (FPT, 2019)

Characterizing Energetic Dependence of Low-Energy Neutron-induced MCUs in 65 nm bulk SRAMs. - Wang Liao; Kojiro Ito; Yukio Mitsuyama; Masanori Hashimoto (IRPS, 2020)

33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications. - Masanori Hashimoto; Xu Bai; Naoki Banno; Munehiro Tada; Toshitsugu Sakamoto; Jaehoon Yu; Ryutaro Doi; Yusuke Araki; Hidetoshi Onodera; Takashi Imagawa; Hiroyuki Ochi; Kazutoshi Wakabayashi; et al. (ISSCC, 2020)

Measurement of Variations in FPGAs under Various Load Conditions. - Yukio Mitsuyama; Takashi Asada; Makio Eguchi (IPSJ Trans. Syst. LSI Des. Methodol., 2020)

Development of Autonomous Driving System based on Image Recognition using Programmable SoCs. - Ryohei Yamamoto; Yuki Izumi; Ryo Aono; Takumi Nagahara; Tomonari Tanaka; Wang Liao; Yukio Mitsuyama (FPT, 2021)