Live Demonstration: Automatic Synthesis of Algorithms on Multi Chip/FPGA with Communication Constraints. - Tomohiro Maruoka; Yukio Miyasaka; Akihiro Goda; Amir Masoud Gharehbaghi; Masahiro Fujita (ISCAS, 2019)

Synthesis of Algorithm Considering Communication Structure of Distributed/Parallel Computing. - Yukio Miyasaka; Ashish Mittal; Masahiro Fujita (ISQED, 2019)

Synthesis and Optimization of Multiple Portions of Circuits for ECO based on Set-Covering and QBF Formulations. - Masahiro Fujita; Yusuke Kimura; Xingming Le; Yukio Miyasaka; Amir Masoud Gharehbaghi (DATE, 2020)

Synthesis and Generalization of Parallel Algorithms Considering Communication Constraints. - Akihiro Goda; Yukio Miyasaka; Amir Masoud Gharehbaghi; Masahiro Fujita (ISQED, 2020)

SAT-Based Data-Flow Mapping Onto Array Processor. - Yukio Miyasaka; Masahiro Fujita (VLSI-SOC, 2020)

SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays. - Yukio Miyasaka; Masahiro Fujita; Alan Mishchenko; John Wawrzynek (VLSI-SoC (Selected Papers), 2020)

Synthesis and Generalization of Parallel Algorithm for Matrix-vector Multiplication. - Yukio Miyasaka; Akihiro Goda; Ashish Mittal; Masahiro Fujita (IPSJ Trans. Syst. LSI Des. Methodol., 2020)

Logic Synthesis for Generalization and Learning Addition. - Yukio Miyasaka; Xinpei Zhang; Mingfei Yu; Qingyang Yi; Masahiro Fujita (DATE, 2021)

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. - Shubham Rai; Walter Lau Neto; Yukio Miyasaka; Xinpei Zhang; Mingfei Yu; Qingyang Yi; Masahiro Fujita; Guilherme B. Manske; Matheus F. Pontes; Leomar S. da Rosa; Marilton S. de Aguiar; Paulo F. Butzen; et al. (DATE, 2021)

Parallel Scheduling Attention Mechanism: Generalization and Optimization. - Mingfei Yu; Yukio Miyasaka; Masahiro Fujita (IPSJ Trans. Syst. LSI Des. Methodol., 2022)

Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams. - Jitendra Kumar; Yukio Miyasaka; Asutosh Srivastava; Masahiro Fujita (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Transduction Method for AIG Minimization. - Yukio Miyasaka (ASPDAC, 2024)

Synthesis of LUT Networks for Random-Looking Dense Functions with Don't Cares - Towards Efficient FPGA Implementation of DNN. - Yukio Miyasaka; Alan Mishchenko; John Wawrzynek; Nicholas J. Fraser (FCCM, 2024)

High-Effort Logic Synthesis Using Randomized Transduction. - Yukio Miyasaka; Alan Mishchenko; John Wawrzynek; Dino Ruic; Xiaoqing Xu (ASP-DAC, 2025)

Bias by Design: Diversity Quantification to Mitigate Structural Bias Effects in AIG Logic Optimization. - Isabella Venancia Gardner; Marcel Walter; Yukio Miyasaka; Robert Wille; Michael Cochez (DATE, 2025)