A multiplier-accumulator macro for a 45 MIPS embedded RISC processor. - Hiroalti Murakami; Naoka Yano; Yukio Ootaguro; Yukio Sugeno; Maki Ueno; Yukinori Muroya; Tsuneo Aramaki (IEEE J. Solid State Circuits, 1996)

300MHz design methodology of VU for emotion synthesis. - Takayuki Kamei; Hideaki Takeda 002; Yukio Ootaguro; Takayoshi Shimazawa; Kazuhiko Tachibana; Shin'ichi Kawakami; Seiji Norimatsu; Fujio Ishihara; Toshinori Sato; Hiroaki Murakami; Nobuhiro Ide; Yukio Endo; et al. (ASP-DAC, 2000)

Utilizing surplus timing for power reduction. - Mototsugu Hamada; Yukio Ootaguro; Tadahiro Kuroda (CICC, 2001)