A built-in test for functional testing in semiconductor random access memory. - Yukiya Miura; Hideo Tamamoto; Yuichi Narita (Syst. Comput. Jpn., 1987)

Built - in concurrent testing for semiconductor random access memories by concurrently testing cells on a word-line. - Yukiya Miura; Hideo Tamamoto; Yuichi Narita (Syst. Comput. Jpn., 1988)

Circuit Design for Built-in Current Testing. - Yukiya Miura; Kozo Kinoshita (ITC, 1992)

Design of testing circuit and test generation for built-in current testing. - Yukiya Miura; Yasushi Wada; Kozo Kinoshita (Syst. Comput. Jpn., 1993)

A Case Study of Mixed-Signal Integrated Circuit Testing: An Application of Current Testing Using the Upper Limit and the Lower Limit. - Yukiya Miura; Sachio Naito; Kozo Kinoshita (ISCAS, 1994)

A Comparative Analysis of Input Stimuli for Testing Mixed-Signal LSIs Based on Curent Testing. - Yukiya Miura (ITC, 1995)

A Method of Current Testing for CMOS Digital and Mixed-Signal LSIs. - Yukiya Miura; Sachio Naito (IEICE Trans. Inf. Syst., 1995)

Real-Time Current Testing for A/D Converters. - Yukiya Miura (IEEE Des. Test Comput., 1996)

An IDDQ Sensor Circuit for Low-Voltage ICs. - Yukiya Miura (ITC, 1997)

A High-Speed IDDQ Sensor for Low-Voltage ICs. - Masaki Hashizume; Yukiya Miura; Masahiro Ichimiya; Takeomi Tamesada; Kozo Kinoshita (Asian Test Symposium, 1998)

Procedure to Overcome the Byzantine General's Problem for Bridging Faults in CMOS Circuits. - Arabi Keshk; Kozo Kinoshita; Yukiya Miura (Asian Test Symposium, 1999)

IDDQ Current Dependency on Test Vectors and Bridging Resistance. - Arabi Keshk; Kozo Kinoshita; Yukiya Miura (Asian Test Symposium, 1999)

A Low-Loss Built-In Current Sensor. - Yukiya Miura; Hiroshi Yamazaki (J. Electron. Test., 1999)

Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits. - Arabi Keshk; Yukiya Miura; Kozo Kinoshita (Asian Test Symposium, 2000)

IDDQ Sensing Technique for High Speed IDDQ Testing. - Teppei Takeda; Masaki Hashizume; Masahiro Ichimiya; Hiroyuki Yotsuyanagi; Yukiya Miura; Kozo Kinoshita (Asian Test Symposium, 2001)

Internal feedback bridging faults in combinational CMOS circuits: analysis and testing. - Yukiya Miura; Shuichi Seno (ETW, 2001)

Proposal of an Operation-Region Model for Analyzing Analog and Mixed-Signal Circuits. - Yukiya Miura (LATW, 2001)

Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits. - Yukiya Miura; Shuichi Seno (J. Electron. Test., 2002)

A BIST Circuit for IDDQ Tests. - Masaki Hashizume; Teppei Takeda; Hiroyuki Yotsuyanagi; Takeomi Tamesada; Yukiya Miura; Kozo Kinoshita (Asian Test Symposium, 2003)

Analysis and Testing of Analog and Mixed-Signal Circuits by an Operation-Region Model: A Case Study of Application and Implementation. - Yukiya Miura; Daisuke Kato (DFT, 2003)

Fault Diagnosis of Analog Circuits by Operation-Region Model and X-Y Zoning Method. - Yukiya Miura (DFT, 2004)

Analysis and Testing of Bridging Faults in CMOS Synchronous Sequential Circuits. - Yukiya Miura (IEICE Trans. Inf. Syst., 2004)

Characteristics of Fault Diagnosis for Analog Circuits Based on Preset Test. - Yukiya Miura (DFT, 2005)

Detection of Interconnect Open Faults with Unknown Values by Ramp Voltage Application. - Yukiya Miura (ATS, 2006)

A BIC Sensor Capable of Adjusting IDDQ Limit in Tests. - Masato Nakanishi; Masaki Hashizume; Hiroyuki Yotsuyanagi; Yukiya Miura (ATS, 2006)

Current Testable Design of Resistor String DACs. - Masaki Hashizume; Tomomi Nishida; Hiroyuki Yotsuyanagi; Takeomi Tamesada; Yukiya Miura (DELTA, 2006)

Fault Diagnosis of Analog Circuits Based on Adaptive Test and Output Characteristics. - Yukiya Miura; Jiro Kato (DFT, 2006)

Proposal of Fault Diagnosis of Analog Circuits by Combining Operation-Region Model and X-Y Zoning Method: Case Study. - Yukiya Miura (J. Electron. Test., 2006)

Current Testable Design of Resistor String DACs. - Masaki Hashizume; Yutaka Hata; Tomomi Nishida; Hiroyuki Yotsuyanagi; Yukiya Miura (ATS, 2007)

Dependable clock distribution for crosstalk aware design. - Yukiya Miura (ITC, 2007)

Diagnosis of Analog Circuits by Using Multiple Transistors and Data Sampling. - Yukiya Miura; Jiro Kato (DFT, 2008)

Adaptive Fault Diagnosis of Analog Circuits by Operation-Region Model and X - Y Zoning Method. - Yukiya Miura; Jiro Kato (J. Electron. Test., 2008)

Ramp Voltage Testing for Detecting Interconnect Open Faults. - Yukiya Miura (IEICE Trans. Inf. Syst., 2008)

On estimation of NBTI-Induced delay degradation. - Mitsumasa Noda; Seiji Kajihara; Yasuo Sato; Kohei Miyase; Xiaoqing Wen; Yukiya Miura (ETS, 2010)

Dual Edge Triggered Flip-Flops for Noise Aware Design. - Yukiya Miura (ETS, 2011)

A supply current testable register string DAC of decoder type. - Masaki Hashizume; Yutaka Hata; Hiroyuki Yotsuyanagi; Yukiya Miura (ISCIT, 2011)

Dual Edge Triggered Flip-Flops for Noise Blocking and Application to Signal Delay Detection. - Yoshihiro Ohkawa; Yukiya Miura (Asian Test Symposium, 2012)

On-chip temperature and voltage measurement for field testing. - Yukiya Miura; Yasuo Sato; Yousuke Miyake; Seiji Kajihara (ETS, 2012)

DART: Dependable VLSI test architecture and its implementation. - Yasuo Sato; Seiji Kajihara; Tomokazu Yoneda; Kazumi Hatayama; Michiko Inoue; Yukiya Miura; Satosni Untake; Takumi Hasegawa; Motoyuki Sato; Kotaro Shimamura (ITC, 2012)

An On-Chip Digital Environment Monitor for Field Test. - Seiji Kajihara; Yousuke Miyake; Yasuo Sato; Yukiya Miura (ATS, 2014)

Temperature and Voltage Estimation Using Ring-Oscillator-Based Monitor for Field Test. - Yousuke Miyake; Yasuo Sato; Seiji Kajihara; Yukiya Miura (ATS, 2014)

A noise-tolerant master-slave flip-flop. - Yukiya Miura; Yoshihiro Ohkawa (IOLTS, 2014)

LSI aging estimation using ring oscillators. - Yukiya Miura; Tatsunori Ikeda (ETS, 2015)

Temperature and Voltage Measurement for Field Test Using an Aging-Tolerant Monitor. - Yousuke Miyake; Yasuo Sato; Seiji Kajihara; Yukiya Miura (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Simulation-based analysis of FF behavior in presence of power supply noise. - Yukiya Miura; Takuya Yamamoto (IOLTS, 2017)

Development of FF Circuits for Measures Against Power Supply Noise. - Yukiya Miura; Miyuki Inoue; Yuya Kinoshita (IOLTS, 2019)

Soft Error Tolerance of Power-Supply-Noise Hardened Latches. - Yukiya Miura; Yuya Kinoshita (IOLTS, 2020)

On-Chip Delay Measurement for Degradation Detection And Its Evaluation under Accelerated Life Test. - Yousuke Miyake; Takaaki Kato; Seiji Kajihara; Masao Aso; Haruji Futami; Satoshi Matsunaga; Yukiya Miura (IOLTS, 2020)

Innovative Test Practices in Asia. - Takeshi Iwasaki; Masao Aso; Haruji Futami; Satoshi Matsunaga; Yousuke Miyake; Takaaki Kato; Seiji Kajihara; Yukiya Miura; Smith Lai; Gavin Hung; Harry H. Chen; Haruo Kobayashi 001; et al. (VTS, 2020)

A Method for Measuring Process Variations in the FPGA Chip Considering the Effect of Wire Delay. - Yukiya Miura; Shingo Tsutsumi (IOLTS, 2021)

Improving Data Sampling Efficiency of Sensitivity Analysis Based on Bilevel Multi-objective Evolutionary Algorithm. - Takuya Hakoishi; Tomohiro Harada; Yukiya Miura (SCIS/ISIS, 2022)

Differential Evolution Using Surrogate Model Based on Pairwise Ranking Estimation for Constrained Optimization Problems. - Hitomi Kano; Tomohiro Harada; Yukiya Miura (SCIS/ISIS, 2022)

Hybrid Rocket Engine Design Using Pairwise Ranking Surrogate-assisted Differential Evolution. - Hitomi Kano; Tomohiro Harada; Yukiya Miura; Masahiro Kanazaki (GECCO Companion, 2023)

Emergence of Cooperative Automated Driving Control at Roundabouts Using Deep Reinforcement Learning. - Reo Nakaya; Tomohiro Harada; Yukiya Miura; Kiyohiko Hattori; Johei Matsuoka (SICE, 2023)

Analysis of the Impact of Prediction Accuracy on Search Performance in Surrogate-assisted Evolutionary Algorithms. - Yuki Hanawa; Tomohiro Harada; Yukiya Miura (CEC, 2024)

Cooperative Autonomous Driving Control among Vehicles of Different Sizes Using Deep Reinforcement Learning. - Akito Takenaka; Tomohiro Harada; Yukiya Miura; Kiyohiko Hattori; Johei Matuoka (IJCNN, 2024)

Impact of surrogate model accuracy on performance and model management strategy in surrogate-assisted evolutionary algorithms. - Yuki Hanawa; Tomohiro Harada; Yukiya Miura (Array, 2025)