Function Call Optimization in Behavioral Synthesis. - Yuko Hara; Hiroyuki Tomiyama; Shinya Honda; Hiroaki Takada (DSD, 2006)

Complexity-constrainted partitioning of sequential programs for efficient behavioral synthesis. - Yuko Hara; Hiroyuki Tomiyama; Shinya Honda; Hiroaki Takada; Katsuya Ishii (ACM Great Lakes Symposium on VLSI, 2007)

Behavioral Synthesis of Double-Precision Floating-Point Adders with Function-Level Transformations: A Case Study. - Yuko Hara; Hiroyuki Tomiyama; Shinya Honda; Hiroaki Takada; Katsuya Ishii (ICESS, 2007)

Function Call Optimization for Efficient Behavioral Synthesis. - Yuko Hara; Hiroyuki Tomiyama; Shinya Honda; Hiroaki Takada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis. - Yuko Hara; Hiroyuki Tomiyama; Shinya Honda; Hiroaki Takada; Katsuya Ishii (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

CHStone: A benchmark program suite for practical C-based high-level synthesis. - Yuko Hara; Hiroyuki Tomiyama; Shinya Honda; Hiroaki Takada; Katsuya Ishii (ISCAS, 2008)

Embedded System Covalidation with RTOS Model and FPGA. - Seiya Shibata; Shinya Honda; Yuko Hara; Hiroyuki Tomiyama; Hiroaki Takada (IPSJ Trans. Syst. LSI Des. Methodol., 2008)

Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis. - Yuko Hara; Hiroyuki Tomiyama; Shinya Honda; Hiroaki Takada (J. Inf. Process., 2009)

Aggressive Register Unsharing Based on SSA Transformation for Clock Enhancement in High-Level Synthesis. - Toshinobu Matsuba; Yuko Hara; Hiroyuki Tomiyama; Shinya Honda; Hiroaki Takada (DELTA, 2010)

Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism. - Yuko Hara; Hiroyuki Tomiyama; Shinya Honda; Hiroaki Takada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Clock-constrained simultaneous allocation and binding for multiplexer optimization in high-level synthesis. - Yuko Hara; Hiroyuki Tomiyama (ASP-DAC, 2012)

ISI at ImageCLEF 2012: Scalable System for Image Annotation. - Yoshitaka Ushiku; Hiroshi Muraoka; Sho Inaba; Teppei Fujisawa; Koki Yasumoto; Naoyuki Gunji; Takayuki Higuchi; Yuko Hara; Tatsuya Harada; Yasuo Kuniyoshi (CLEF (Online Working Notes/Labs/Workshop), 2012)

Selective Resource Sharing with RT-Level Retiming for Clock Enhancement in High-Level Synthesis. - Yuko Hara-Azumi; Toshinobu Matsuba; Hiroyuki Tomiyama; Shinya Honda; Hiroaki Takada (HPCC-ICESS, 2012)

A redundant wire addition method for Patchable Accelerator. - Masayuki Wakizaka; Hiroaki Yoshida; Yuko Hara-Azumi; Shigeru Yamashita (ICECS, 2012)

Task mapping techniques for embedded many-core SoCs. - Junya Kaida; Takuji Hieda; Ittetsu Taniguchi; Hiroyuki Tomiyama; Yuko Hara-Azumi; Koji Inoue (ISOCC, 2012)

A clique-based approach to find binding and scheduling result in flow-based microfluidic biochips. - Trung Anh Dinh; Shigeru Yamashita; Tsung-Yi Ho; Yuko Hara-Azumi (ASP-DAC, 2013)

VISA synthesis: Variation-aware Instruction Set Architecture synthesis. - Yuko Hara-Azumi; Takuya Azumi; Nikil D. Dutt (ASP-DAC, 2013)

Instruction-set extension under process variation and aging effects. - Yuko Hara-Azumi; Farshad Firouzi; Saman Kiamehr; Mehdi Baradaran Tahoori (DATE, 2013)

TECSCE: HW/SW Codesign Framework for Data Parallelism Based on Software Component. - Takuya Azumi; Yasaman Samei Syahkal; Yuko Hara-Azumi; Hiroshi Oyama 002; Rainer Dömer (IESS, 2013)

Cost-efficient scheduling in high-level synthesis for Soft-Error Vulnerability Mitigation. - Yuko Hara-Azumi; Hiroyuki Tomiyama (ISQED, 2013)

Selective Check of Data-Path for Effective Fault Tolerance. - Tanvir Ahmed 004; Jun Yao 001; Yuko Hara-Azumi; Shigeru Yamashita; Yasuhiko Nakashima (IEICE Trans. Inf. Syst., 2013)

Clique-Based Architectural Synthesis of Flow-Based Microfluidic Biochips. - Trung Anh Dinh; Shigeru Yamashita; Tsung-Yi Ho; Yuko Hara-Azumi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Static Mapping of Multiple Data-Parallel Applications on Embedded Many-Core SoCs. - Junya Kaida; Yuko Hara-Azumi; Takuji Hieda; Ittetsu Taniguchi; Hiroyuki Tomiyama; Koji Inoue (IEICE Trans. Inf. Syst., 2013)

Quantitative Evaluation of Resource Sharing in High-level Synthesis Using Realistic Benchmarks. - Yuko Hara-Azumi; Toshinobu Matsuba; Hiroyuki Tomiyama; Shinya Honda; Hiroaki Takada (IPSJ Trans. Syst. LSI Des. Methodol., 2013)

Emulator-oriented tiny processors for unreliable post-silicon devices: A case study. - Yuko Hara-Azumi; Masaya Kunimoto; Yasuhiko Nakashima (ASP-DAC, 2014)

Better-Than-DMR Techniques for Yield Improvement. - Shunichi Sanae; Yuko Hara-Azumi; Shigeru Yamashita; Yasuhiko Nakashima (FCCM, 2014)

Differing effects of attention in single-units and populations are well predicted by heterogeneous tuning and the normalization model of attention. - Yuko Hara; Franco Pestilli; Justin L. Gardner (Frontiers Comput. Neurosci., 2014)

Static Mapping with Dynamic Switching of Multiple Data-Parallel Applications on Embedded Many-Core SoCs. - Ittetsu Taniguchi; Junya Kaida; Takuji Hieda; Yuko Hara-Azumi; Hiroyuki Tomiyama (IEICE Trans. Inf. Syst., 2014)

Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs. - Yuko Hara-Azumi; Toshinobu Matsuba; Hiroyuki Tomiyama; Shinya Honda; Hiroaki Takada (IPSJ Trans. Syst. LSI Des. Methodol., 2014)

Timing speculation-aware instruction set extension for resource-constrained embedded systems. - Tanvir Ahmed 004; Yuko Hara-Azumi (ASAP, 2015)

Profiling-driven multi-cycling in FPGA high-level synthesis. - Stefan Hadjis; Andrew Canis; Ryoya Sobue; Yuko Hara-Azumi; Hiroyuki Tomiyama; Jason Helge Anderson (DATE, 2015)

Synthesizable-from-C Embedded Processor Based on MIPS-ISA and OISC. - Tanvir Ahmed 004; Noriaki Sakamoto; Jason Helge Anderson; Yuko Hara-Azumi (EUC, 2015)

A systematic methodology for design and analysis of approximate array multipliers. - Takahiro Yamamoto; Ittetsu Taniguchi; Hiroyuki Tomiyama; Shigeru Yamashita; Yuko Hara-Azumi (APCCAS, 2016)

Effect of LFSR seeding, scrambling and feedback polynomial on stochastic computing accuracy. - Jason Helge Anderson; Yuko Hara-Azumi; Shigeru Yamashita (DATE, 2016)

CGRA-ME: A unified framework for CGRA modelling and exploration. - S. Alexander Chin; Noriaki Sakamoto; Allan Rui; Jim Zhao; Jin Hee Kim; Yuko Hara-Azumi; Jason Helge Anderson (ASAP, 2017)

Approximate data reuse-based processor: a case study on image compression. - Hisashi Osawa; Yuko Hara-Azumi (ESTIMedia, 2017)

One-instruction set computer-based multicore processors for energy-efficient streaming data processing. - Minato Yokota; Kaoru Saso; Yuko Hara-Azumi (RSP, 2017)

Subleq⊝: An Area-Efficient Two-Instruction-Set Computer. - Noriaki Sakamoto; Tanvir Ahmed 004; Jason Helge Anderson; Yuko Hara-Azumi (IEEE Embed. Syst. Lett., 2017)

A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers. - Takahiro Yamamoto; Ittetsu Taniguchi; Hiroyuki Tomiyama; Shigeru Yamashita; Yuko Hara-Azumi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Simple Instruction-Set Computer for Area and Energy-Sensitive IoT Edge Devices. - Kaoru Saso; Yuko Hara-Azumi (ASAP, 2018)

FPGA-Based amoeba-inspired SAT solver for cyber-physical systems. - Anh Hoang Ngoc Nguyen; Masashi Aono; Yuko Hara-Azumi (ICCPS, 2019)

Amoeba-Inspired Hardware SAT Solver with Effective Feedback Control. - Anh Hoang Ngoc Nguyen; Masashi Aono; Yuko Hara-Azumi (FPT, 2019)

Maximum Error-Aware Design of Approximate Array Multipliers. - Kenta Shirane; Takahiro Yamamoto; Ittetsu Taniguchi; Yuko Hara-Azumi; Shigeru Yamashita; Hiroyuki Tomiyama (ISOCC, 2019)

Amoeba-Inspired Stochastic Hardware SAT Solver. - Kazuaki Hara; Naoki Takeuchi; Masashi Aono; Yuko Hara-Azumi (ISQED, 2019)

SSA-AC: Static Significance Analysis for Approximate Computing. - Sara Ayman Metwalli; Yuko Hara-Azumi (ACM Trans. Design Autom. Electr. Syst., 2019)

Approximate Data Reuse-based Accelerator Design for Embedded Processor. - Hisashi Osawa; Yuko Hara-Azumi (ACM Trans. Design Autom. Electr. Syst., 2019)

Real-Time Routing for Wireless Relay Fronthaul with Vehicle-Mounted Radio Units. - Yu Nakayama; Yuko Hara-Azumi; Anh Hoang Ngoc Nguyen; Daisuke Hisano; Yoshiaki Inoue; Takayuki Nishio; Kazuki Maruta (VTC Spring, 2020)

APNAS: Accuracy-and-Performance-Aware Neural Architecture Search for Neural Hardware Accelerators. - Paniti Achararit; Muhammad Abdullah Hanif; Rachmad Vidya Wicaksana Putra; Muhammad Shafique 001; Yuko Hara-Azumi (IEEE Access, 2020)

FPGA-Based Hardware/Software Co-Design of a Bio-Inspired SAT Solver. - Anh Hoang Ngoc Nguyen; Masashi Aono; Yuko Hara-Azumi (IEEE Access, 2020)

Implementation of Lightweight eHealth Applications on a Low-Power Embedded Processor. - Mingyu Yang; Yuko Hara-Azumi (IEEE Access, 2020)

Revisiting Simple and Energy Efficient Embedded Processor Designs Toward the Edge Computing. - Kaoru Saso; Yuko Hara-Azumi (IEEE Embed. Syst. Lett., 2020)

A Circuit-Level Amoeba-Inspired SAT Solver. - Naoki Takeuchi; Masashi Aono; Yuko Hara-Azumi; Christopher L. Ayala (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Revisiting System Noise in Side-Channel Attacks: Mutual Assistant SCA vs. Genetic Algorithm. - Rei Kudo; Takeshi Sugawara 001; Kazuo Sakiyama; Yuko Hara-Azumi; Yang Li 001 (AsianHOST, 2021)

Zero Correlation Error: A Metric for Finite-Length Bitstream Independence in Stochastic Computing. - Hsuan Hsiao; Joshua San Miguel; Yuko Hara-Azumi; Jason Helge Anderson (ASP-DAC, 2021)

An FPGA-based Stochastic SAT Solver Leveraging Inter-Variable Dependencies. - Anh Hoang Ngoc Nguyen; Yuko Hara-Azumi (FPL, 2021)

Deep Joint Source-Channel Coding and Modulation for Underwater Acoustic Communication. - Yoshiaki Inoue; Daisuke Hisano; Kazuki Maruta; Yuko Hara-Azumi; Yu Nakayama (GLOBECOM, 2021)

Improved Step Detection with Smartphone Handheld Mode Recognition. - Warnnaphorn Suksuganjana; Seksan Laitrakun; Krit Athikulwongse; Yuko Hara-Azumi; Somrudee Deepaisarn (KST, 2021)

Space- Time- Domain Adaptive Equalizer Employed Successive Interference Cancellation for Underwater Acoustic Communication. - Kosuke Suzuoki; Daisuke Hisano; Kazuki Maruta; Yoshiaki Inoue; Yuko Hara-Azumi; Yu Nakayama (VTC Fall, 2021)

Real-Time Reconfiguration of Time-Aware Shaper for ULL Transmission in Dynamic Conditions. - Yu Nakayama; Ryo Yaegashi; Anh Hoang Ngoc Nguyen; Yuko Hara-Azumi (IEEE Access, 2021)

Hardware SAT Solver-based Area-efficient Accelerator for Autonomous Driving. - Yusuke Inuma; Yuko Hara-Azumi (FPT, 2022)

A Self-Attention Network for Deep JSCCM: The Design and FPGA Implementation. - Shohei Fujimaki; Yoshiaki Inoue; Daisuke Hisano; Kazuki Maruta; Yu Nakayama; Yuko Hara-Azumi (GLOBECOM, 2022)

Optimized Software Implementations of Ascon, Grain-128AEAD, and TinyJambu on ARM Cortex-M0. - Tomoaki Kitahara; Ryota Hira; Yuko Hara-Azumi; Daiki Miyahara; Yang Li 001; Kazuo Sakiyama (CANDARW, 2022)

Examining Vulnerability of HLS-designed Chaskey-12 Circuits to Power Side-Channel Attacks. - Saya Inagaki; Mingyu Yang; Yang Li 001; Kazuo Sakiyama; Yuko Hara-Azumi (ISQED, 2022)

Gossip Swap SGD: Lightweight Decentralized Machine Learning for Non-Homogeneous Data Distribution. - Naoya Yokota; Yuko Hara-Azumi (SoMeT, 2022)

Aquatic Fronthaul for Underwater-Ground Communication in 6G Mobile Communications. - Ayano Higuchi; Erina Takeshita; Daisuke Hisano; Yoshiaki Inoue; Kazuki Maruta; Takayuki Nishio; Yuko Hara-Azumi; Yu Nakayama (VTC Spring, 2022)

Stochastic Image Transmission with CoAP for Extreme Environments. - Erina Takeshita; Asahi Sakaguchi; Daisuke Hisano; Yoshiaki Inoue; Kazuki Maruta; Yuko Hara-Azumi; Yu Nakayama (VTC Spring, 2022)

Multimodal Neural Network Acceleration on a Hybrid CPU-FPGA Architecture: A Case Study. - Mehdi Trabelsi Ajili; Yuko Hara-Azumi (IEEE Access, 2022)

Real-Time Resource Allocation in Passive Optical Network for Energy-Efficient Inference at GPU-Based Network Edge. - Yu Nakayama; Yukito Onodera; Anh Hoang Ngoc Nguyen; Yuko Hara-Azumi (IEEE Internet Things J., 2022)

Introduction to the Special Section on High-level Synthesis for FPGA: Next-generation Technologies and Applications. - Christian Pilato; Zhenman Fang; Yuko Hara-Azumi; Jim Hwang (ACM Trans. Design Autom. Electr. Syst., 2022)

On the Practical Dependency of Fresh Randomness in AES S-box with Second-Order TI. - Maki Tsukahara; Haruka Hirata; Mingyu Yang; Daiki Miyahara; Yang Li 001; Yuko Hara-Azumi; Kazuo Sakiyama (CANDARW, 2023)

Impact of Quantization Noise on CNN-based Joint Source-Channel Coding and Modulation. - Keigo Matsumoto; Yoshiaki Inoue; Yuko Hara-Azumi; Kazuki Maruta; Yu Nakayama; Daisuke Hisano (CCNC, 2023)

Convergence Improvement by Parameters Exchange in Asynchronous Decentralized Federated Learning for Non-IID Data. - Asato Yamazaki; Takayuki Nishio; Yuko Hara-Azumi (SEAA, 2023)

Power Side-channel Countermeasures for ARX Ciphers using High-level Synthesis. - Saya Inagaki; Mingyu Yang; Yang Li 001; Kazuo Sakiyama; Yuko Hara-Azumi (FPGA, 2023)

Dynamic Split Computing-Aware Mixed-Precision Quantization for Efficient Deep Edge Intelligence. - Naoki Nagamatsu; Yuko Hara-Azumi (TrustCom, 2023)

Implementation of Deep Joint Source-Channel Coding on 5G Systems for Image Transmission. - Keigo Matsumoto; Yoshiaki Inoue; Yuko Hara-Azumi; Kazuki Maruta; Yu Nakayama; Yoshinori Shinohara; Hiroki Ikeda; Daisuke Hisano (VTC Fall, 2023)

Software Evaluation for Second Round Candidates in NIST Lightweight Cryptography. - Ryota Hira; Tomoaki Kitahara; Daiki Miyahara; Yuko Hara-Azumi; Yang Li 001; Kazuo Sakiyama (J. Inf. Process., 2023)

Power Side-channel Attack Resistant Circuit Designs of ARX Ciphers Using High-level Synthesis. - Saya Inagaki; Mingyu Yang; Yang Li 022; Kazuo Sakiyama; Yuko Hara-Azumi (ACM Trans. Embed. Comput. Syst., 2023)

Yet Another Physical Leakage Assessment with the Wasserstein Distance. - Haruka Hirata; Yusaku Harada; Yuko Hara; Kazuo Sakiyama; Yang Li 001 (AsianHOST, 2024)

PreLock: Precision Locking for Protecting Embedded Processor. - Tomosuke Ichioka; Yohei Watanabe 001; Yuko Hara (AsianHOST, 2024)

Tram-FL: Routing-based Model Training for Decentralized Federated Learning. - Kota Maejima; Takayuki Nishio; Asato Yamazaki; Yuko Hara-Azumi (CCNC, 2024)

High-Level Synthesis Countermeasure Using Threshold Implementation with Mixed Number of Shares. - Gento Hiruma; Mingyu Yang; Yang Li 022; Kazuo Sakiyama; Yuko Hara-Azumi (HEART, 2024)

A Comparative Study of Loss Functions for Arbitrary-Oriented Object Detection in Aerial Images. - Kaung Htet San; Toshiaki Kondo; Sanparith Marukatat; Yuko Hara-Azumi (JCSSE, 2024)

Multiplicative Masked M&M: An Attempt at Combined Countermeasures with Reduced Randomness. - Kaiyuan Li; Haruka Hirata; Daiki Miyahara; Kazuo Sakiyama; Yuko Hara; Yang Li 001 (TrustCom, 2024)

Mixed-Precision Neural Architecture Search and Dynamic Split Point Selection for Split Computing. - Naoki Nagamatsu; Kenshiro Ise; Yuko Hara (IEEE Access, 2024)

Hardware/Software Cooperative Design Against Power Side-Channel Attacks on IoT Devices. - Mingyu Yang; Tanvir Ahmed 004; Saya Inagaki; Kazuo Sakiyama; Yang Li; Yuko Hara-Azumi (IEEE Internet Things J., 2024)

Hardware/Software Codesign of Real-Time Intrusion Detection System for Internet of Things Devices. - Qingyu Zeng; Yuko Hara-Azumi (IEEE Internet Things J., 2024)

PSYLOCKE: Provably Secure Logic Locking with Practical Efficiency. - Yohei Watanabe 001; Kyoichi Asano; Haruka Hirata; Tomoki Ono; Mingyu Yang; Mitsugu Iwamoto; Yang Li 001; Yuko Hara (IACR Cryptol. ePrint Arch., 2025)

Practical Randomness Effects on Physical Security in Second-Order Threshold Implementation of AES. - Maki Tsukahara; Yusaku Harada; Haruka Hirata; Daiki Miyahara; Yang Li 001; Yuko Hara-Azumi; Kazuo Sakiyama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2025)

5G Indoor/Outdoor Field Trial of Deep Joint Source-Channel Coding Method. - Daisuke Hisano; Keigo Matsumoto; Yoshiaki Inoue; Yuko Hara; Kazuki Maruta; Yu Nakayama; Hiroshi Tatsukawa; Yuji Kawai; Yoshinori Shinohara; Hiroki Ikeda (IEEE Open J. Commun. Soc., 2025)