Input-Splitting of Large Neural Networks for Power-Efficient Accelerator with Resistive Crossbar Memory Array. - Yulhwa Kim; Hyungjun Kim; Daehyun Ahn; Jae-Joon Kim (ISLPED, 2018)

Compact Convolution Mapping on Neuromorphic Hardware using Axonal Delay. - Jinseok Kim 004; Yulhwa Kim; Sungho Kim; Jae-Joon Kim (ISLPED, 2018)

Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators. - Yulhwa Kim; Hyungjun Kim; Jae-Joon Kim (CoRR, 2018)

In-memory batch-normalization for resistive memory based binary neural network hardware. - Hyungjun Kim; Yulhwa Kim; Jae-Joon Kim (ASP-DAC, 2019)

Effect of Device Variation on Mapping Binary Neural Network to Memristor Crossbar Array. - Wooseok Yi; Yulhwa Kim; Jae-Joon Kim (DATE, 2019)

Area-Efficient and Variation-Tolerant In-Memory BNN Computing using 6T SRAM Array. - Jinseok Kim 004; Jongeun Koo; Taesu Kim; Yulhwa Kim; Hyungjun Kim; Seunghyun Yoo; Jae-Joon Kim (VLSI Circuits, 2019)

BitSplit-Net: Multi-bit Deep Neural Network with Bitwise Activation Function. - Hyungjun Kim; Yulhwa Kim; Sungju Ryu; Jae-Joon Kim (CoRR, 2019)

Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning. - Shihui Yin; Jae-sun Seo; Yulhwa Kim; Xu Han; Hugh J. Barnaby; Shimeng Yu; Yandong Luo; Wangxin He; Xiaoyu Sun 001; Jae-Joon Kim (IEEE Micro, 2019)

A 44.1TOPS/W Precision-Scalable Accelerator for Quantized Neural Networks in 28nm CMOS. - Sungju Ryu; Hyungjun Kim; Wooseok Yi; Jongeun Koo; Eunhwan Kim; Yulhwa Kim; Taesu Kim; Jae-Joon Kim (CICC, 2020)

Algorithm/Hardware Co-Design for In-Memory Neural Network Computing with Minimal Peripheral Circuit Overhead. - Hyungjun Kim; Yulhwa Kim; Sungju Ryu; Jae-Joon Kim (DAC, 2020)

Time-step interleaved weight reuse for LSTM neural network computing. - Naebeom Park; Yulhwa Kim; Daehyun Ahn; Taesu Kim; Jae-Joon Kim (ISLPED, 2020)

Single RRAM Cell-based In-Memory Accelerator Architecture for Binary Neural Networks. - Hyunmyung Oh; Hyungjun Kim; Nameun Kang; Yulhwa Kim; Jihoon Park; Jae-Joon Kim (AICAS, 2021)

Energy-efficient charge sharing-based 8T2C SRAM in-memory accelerator for binary neural networks in 28nm CMOS. - Hyunmyung Oh; Hyungjun Kim; Daehyun Ahn; Jihoon Park; Yulhwa Kim; Inhwan Lee; Jae-Joon Kim (A-SSCC, 2021)

Mapping Binary ResNets on Computing-In-Memory Hardware with Low-bit ADCs. - Yulhwa Kim; Hyungjun Kim; Jihoon Park; Hyunmyung Oh; Jae-Joon Kim (DATE, 2021)

Maximizing Parallel Activation of Word-Lines in MRAM-Based Binary Neural Network Accelerators. - Daehyun Ahn; Hyunmyung Oh; Hyungjun Kim; Yulhwa Kim; Jae-Joon Kim (IEEE Access, 2021)

Extreme Partial-Sum Quantization for Analog Computing-In-Memory Neural Network Accelerators. - Yulhwa Kim; Hyungjun Kim; Jae-Joon Kim (ACM J. Emerg. Technol. Comput. Syst., 2022)

BitBlade: Energy-Efficient Variable Bit-Precision Hardware Accelerator for Quantized Neural Networks. - Sungju Ryu; Hyungjun Kim; Wooseok Yi; Eunhwan Kim; Yulhwa Kim; Taesu Kim; Jae-Joon Kim (IEEE J. Solid State Circuits, 2022)

Winning Both the Accuracy of Floating Point Activation and the Simplicity of Integer Arithmetic. - Yulhwa Kim; Jaeyong Jang; Jehun Lee; Jihoon Park; Jeonghoon Kim; Byeongwook Kim; Baeseong Park; Se Jung Kwon; Dongsoo Lee; Jae-Joon Kim (ICLR, 2023)

Leveraging Early-Stage Robustness in Diffusion Models for Efficient and High-Quality Image Synthesis. - Yulhwa Kim; Dongwon Jo; Hyesung Jeon; Taesu Kim; Daehyun Ahn; Hyungjun Kim; Jae-Joon Kim (NeurIPS, 2023)

Squeezing Large-Scale Diffusion Models for Mobile. - Jiwoong Choi; Minkyu Kim; Daehyun Ahn; Taesu Kim; Yulhwa Kim; Dongwon Jo; Hyesung Jeon; Jae-Joon Kim; Hyungjun Kim (CoRR, 2023)

FIGNA: Integer Unit-Based Accelerator Design for FP-INT GEMM Preserving Numerical Accuracy. - Jaeyong Jang; Yulhwa Kim; Juheun Lee; Jae-Joon Kim (HPCA, 2024)

SLEB: Streamlining LLMs through Redundancy Verification and Elimination of Transformer Blocks. - Jiwon Song; Kyungseok Oh; Taesu Kim; Hyungjun Kim; Yulhwa Kim; Jae-Joon Kim (ICML, 2024)

Mixture of Scales: Memory-Efficient Token-Adaptive Binarization for Large Language Models. - Dongwon Jo; Taesu Kim; Yulhwa Kim; Jae-Joon Kim (NeurIPS, 2024)

L4Q: Parameter Efficient Quantization-Aware Training on Large Language Models via LoRA-wise LSQ. - Hyesung Jeon; Yulhwa Kim; Jae-Joon Kim (CoRR, 2024)

L4Q: Parameter Efficient Quantization-Aware Fine-Tuning on Large Language Models. - Hyesung Jeon; Yulhwa Kim; Jae-Joon Kim (ACL (1), 2025)

Column-wise Quantization of Weights and Partial Sums for Accurate and Efficient Compute-In-Memory Accelerators. - Jiyoon Kim; Kang Eun Jeon; Yulhwa Kim; Jong Hwan Ko (DATE, 2025)

Compute-in-Memory Array Design Using Stacked Hybrid IGZO/Si eDRAM cells. - Munhyeon Kim; Yulhwa Kim; Jae-Joon Kim (DATE, 2025)

FastKV: KV Cache Compression for Fast Long-Context Processing with Token-Selective Propagation. - Dongwon Jo; Jiwon Song; Yulhwa Kim; Jae-Joon Kim (CoRR, 2025)

Reasoning Path Compression: Compressing Generation Trajectories for Efficient LLM Reasoning. - Jiwon Song; Dongwon Jo; Yulhwa Kim; Jae-Joon Kim (CoRR, 2025)