Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs. - Kuan-Te Wu; Jin-Fu Li 001; Yun-Chao Yu; Chih-Sheng Hou; Chi-Chun Yang; Ding-Ming Kwai; Yung-Fa Chou; Chih-Yen Lo (ATS, 2014)

A hybrid built-in self-test scheme for DRAMs. - Chi-Chun Yang; Jin-Fu Li 001; Yun-Chao Yu; Kuan-Te Wu; Chih-Yen Lo; Chao-Hsun Chen; Jenn-Shiang Lai; Ding-Ming Kwai; Yung-Fa Chou (VLSI-DAT, 2015)

Hierarchical Test Integration Methodology for 3-D ICs. - Che-Wei Chou; Jin-Fu Li 001; Yun-Chao Yu; Chih-Yen Lo; Ding-Ming Kwai; Yung-Fa Chou (IEEE Des. Test, 2015)