DrowsyNet: Convolutional neural networks with runtime power-accuracy tunability using inference-stage dropout. - Ren-Shuo Liu; Yun-Chen Lo; Yuan-Chun Luo; Chih-Yu Shen; Cheng-Ju Lee (VLSI-DAT, 2018)

Physically Tightly Coupled, Logically Loosely Coupled, Near-Memory BNN Accelerator (PTLL-BNN). - Yun-Chen Lo; Yu-Chun Kuo; Yun-Sheng Chang; Jian-Hao Huang; Jun-Shen Wu; Wen-Chien Ting; Tai-Hsing Wen; Ren-Shuo Liu (ESSCIRC, 2019)

15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips. - Xin Si; Yung-Ning Tu; Wei-Hsing Huang; Jian-Wei Su; Pei-Jung Lu; Jing-Hong Wang; Ta-Wei Liu; Ssu-Yen Wu; Ruhui Liu; Yen-Chi Chou; Zhixiao Zhang; Syuan-Hao Sie; et al. (ISSCC, 2020)

15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices. - Cheng-Xin Xue; Tsung-Yuan Huang; Je-Syu Liu; Ting-Wei Chang; Hui-Yao Kao; Jing-Hong Wang; Ta-Wei Liu; Shih-Ying Wei; Sheng-Po Huang; Wei-Chen Wei; Yi-Ren Chen; Tzu-Hsiang Hsu; et al. (ISSCC, 2020)

Interference-Free Design Methodology for Paper-Based Digital Microfluidic Biochips. - Yun-Chen Lo; Bing Li 005; Sooyong Park; Kwanwoo Shin; Tsung-Yi Ho (ASP-DAC, 2021)

ISSA: Input-Skippable, Set-Associative Computing-in-Memory (SA-CIM) Architecture for Neural Network Accelerators. - Yun-Chen Lo; Chih-Chen Yeh; Jun-Shen Wu; Chia-Chun Wang; Yu-Chih Tsai; Wen-Chien Ting; Ren-Shuo Liu (ICCAD, 2022)

Bit-Serial Cache: Exploiting Input Bit Vector Repetition to Accelerate Bit-Serial Inference. - Yun-Chen Lo; Ren-Shuo Liu (DAC, 2023)

Morphable CIM: Improving Operation Intensity and Depthwise Capability for SRAM-CIM Architecture. - Yun-Chen Lo; Ren-Shuo Liu (DAC, 2023)

BICEP: Exploiting Bitline Inversion for Efficient Operation-Unit-Based Compute-in-Memory Architecture: No Retraining Needed! - Yun-Chen Lo; Chia-Chun Wang; Ren-Shuo Liu (ICCD, 2023)

Exploiting and Enhancing Computation Latency Variability for High-Performance Time-Domain Computing-in-Memory Neural Network Accelerators. - Chia-Chun Wang; Yun-Chen Lo; Jun-Shen Wu; Yu-Chih Tsai; Chia-Cheng Chang; Tsen-Wei Hsu; Min-Wei Chu; Chuan-Yao Lai; Ren-Shuo Liu (ICCD, 2023)

Block and Subword-Scaling Floating-Point (BSFP) : An Efficient Non-Uniform Quantization For Low Precision Inference. - Yun-Chen Lo; Tse-Kuang Lee; Ren-Shuo Liu (ICLR, 2023)

A Nonvolatile Al-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W. - Wei-Hsing Huang; Tai-Hao Wen; Je-Min Hung; Win-San Khwa; Yun-Chen Lo; Chuan-Jia Jhang; Hung-Hsi Hsu; Yu-Hsiang Chin; Yu-Chiao Chen; Chuna-Chuan Lo; Ren-Shuo Liu; Kea-Tiong Tang; et al. (ISSCC, 2023)

Bucket Getter: A Bucket-based Processing Engine for Low-bit Block Floating Point (BFP) DNNs. - Yun-Chen Lo; Ren-Shuo Liu (MICRO, 2023)

LV: Latency-Versatile Floating-Point Engine for High-Performance Deep Neural Networks. - Yun-Chen Lo; Yu-Chih Tsai; Ren-Shuo Liu (IEEE Comput. Archit. Lett., 2023)

Nanoscaling Floating-Point (NxFP): NanoMantissa, Adaptive Microexponents, and Code Recycling for Direct-Cast Compression of Large Language Models. - Yun-Chen Lo; Gu-Yeon Wei; David Brooks 001 (CoRR, 2024)

A Nonvolatile AI-Edge Processor With SLC-MLC Hybrid ReRAM Compute-in-Memory Macro Using Current-Voltage-Hybrid Readout Scheme. - Hung-Hsi Hsu; Tai-Hao Wen; Wei-Hsing Huang; Win-San Khwa; Yun-Chen Lo; Chuan-Jia Jhang; Yu-Hsiang Chin; Yu-Chiao Chen; Chung-Chuan Lo; Ren-Shuo Liu; Kea-Tiong Tang; Chih-Cheng Hsieh; et al. (IEEE J. Solid State Circuits, 2024)

ISSA: Architecting CNN Accelerators Using Input-Skippable, Set-Associative Computing-in-Memory. - Yun-Chen Lo; Jun-Shen Wu; Chia-Chun Wang; Yu-Chih Tsai; Chih-Chen Yeh; Wen-Chien Ting; Ren-Shuo Liu (IEEE Trans. Computers, 2024)