Timing-driven cell placement optimization for early slack histogram compression. - Chau-Chin Huang; Yen-Chun Liu; Yu-Sheng Lu; Yun-Chih Kuo; Yao-Wen Chang; Sy-Yen Kuo (DAC, 2016)

Clock-aware placement for large-scale heterogeneous FPGAs. - Yun-Chih Kuo; Chau-Chin Huang; Shih-Chun Chen; Chun-Han Chiang; Yao-Wen Chang; Sy-Yen Kuo (ICCAD, 2017)

On Pre-Assignment Route Prototyping for Irregular Bumps on BGA Packages. - Jyun-Ru Jiang; Yun-Chih Kuo; Simon Yi-Hung Chen; Hung-Ming Chen (DATE, 2020)

Clock-Aware Placement for Large-Scale Heterogeneous FPGAs. - Jianli Chen; Zhifeng Lin; Yun-Chih Kuo; Chau-Chin Huang; Yao-Wen Chang; Shih-Chun Chen; Chun-Han Chiang; Sy-Yen Kuo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Practical Substrate Design Considering Symmetrical and Shielding Routes. - Hao-Yu Chi; Simon Yi-Hung Chen; Hung-Ming Chen; Chien-Nan Liu; Yun-Chih Kuo; Ya-Hsin Chang; Kuan-Hsien Ho (DATE, 2022)

Substrate Signal Routing Solution Exploration for High-Density Packages with Machine Learning. - Yeu-Haw Yeh; Simon Yi-Hung Chen; Hung-Ming Chen; Deng-Yao Tu; Guan-Qi Fang; Yun-Chih Kuo; Po-Yang Chen (VLSI-DAT, 2022)

DPRoute: Deep Learning Framework for Package Routing. - Yeu-Haw Yeh; Simon Yi-Hung Chen; Hung-Ming Chen; Deng-Yao Tu; Guan-Qi Fang; Yun-Chih Kuo; Po-Yang Chen (ASP-DAC, 2023)