A 24-29.5-GHz Scalable 2 × 2 I-Q TX/RX Chipset With Streamlined IF Interfaces for DBF Systems. - Long Wang; Jixin Chen; Zhe Chen 021; Xiaoyue Xia; Yun Hu 005; Sidou Zheng; Zekun Li 005; Rui Zhou; Peigen Zhou; Jianyi Zhou; Wei Hong 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)