Loop-List Scheduling for Heterogeneous Functional Units. - Yun-Nan Chang; Ching-Yi Wang; Keshab K. Parhi (Great Lakes Symposium on VLSI, 1996)

Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers. - Janardhan H. Satyanarayana; Keshab K. Parhi; Leilei Song; Yun-Nan Chang (ICCD, 1996)

Design and Implementation of Low-Power Digit-Serial Multipliers. - Yun-Nan Chang; Janardhan H. Satyanarayana; Keshab K. Parhi (ICCD, 1997)

High-performance digit-serial complex-number multiplier-accumulator. - Yun-Nan Chang; Keshab K. Parhi (ICCD, 1998)

Heuristic Loop-Based Scheduling and Allocation for DSP Synthesis with Heterogeneous Functional Units. - Yun-Nan Chang; Ching-Yi Wang; Keshab K. Parhi (J. VLSI Signal Process., 1998)

Low-power bit-serial Viterbi decoder for 3rd generation W-CDMA systems. - Hiroshi Suzuki; Yun-Nan Chang; Keshab K. Parhi (CICC, 1999)

Low-power bit-serial Viterbi decoder for next generation wide-band CDMA systems. - Hiroshi Suzuki; Yun-Nan Chang; Keshab K. Parhi (ICASSP, 1999)

A 2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder. - Yun-Nan Chang; Hiroshi Suzuki; Keshab K. Parhi (IEEE J. Solid State Circuits, 2000)

Design of soft-output Viterbi decoders with hybrid trace-back processing. - Yun-Nan Chang (ISCAS (2), 2003)

An efficient pipelined FFT architecture. - Yun-Nan Chang; Keshab K. Parhi (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

An Efficient In-Place VLSI Architecture for Viterbi Algorithm. - Yun-Nan Chang (J. VLSI Signal Process., 2003)

Design of an efficient memory-based DVB-T channel decoder. - Yun-Nan Chang (ISCAS (5), 2005)

An Efficient VLSI Architecture for Normal I/O Order Pipeline FFT Design. - Yun-Nan Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

A low-cost dual-mode deinterleaver design. - Yun-Nan Chang (IEEE Trans. Consumer Electron., 2008)

An Efficient Design of H.264 Inter Interpolator with Bandwidth Optimization. - Yun-Nan Chang; Ting-Chi Tong (J. Signal Process. Syst., 2008)

An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics. - Liang-Bi Chen; Ruei-Ting Gu; Wei-Sheng Huang; Chien-Chou Wang; Wen-Chi Shiue; Tsung-Yu Ho; Yun-Nan Chang; Shen-Fu Hsiao; Chung-Nan Lee; Ing-Jer Huang (ASP-DAC, 2009)

A Lossless Buffer Compression Scheme for 3D Graphic System. - Yun-Nan Chang; Ting-Chi Tong (CGVR, 2009)

A Fast Spline Curve Rendering Accelerator Architecture. - Yun-Nan Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A Multibank Memory-Based VLSI Architecture of DVB Symbol Deinterleaver. - Yun-Nan Chang (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Digit-Serial Pipeline Sorter Architecture. - Yun-Nan Chang (J. Signal Process. Syst., 2010)

Architectures for digital filters using stochastic computing. - Yun-Nan Chang; Keshab K. Parhi (ICASSP, 2013)

Two-level hierarchical fill-buffer for graphics rendering systems. - Yun-Nan Chang (NEWCAS, 2013)

Efficient Vector Graphics Rasterization Accelerator Using Optimized Scan-Line Buffer. - Ting-Chi Tong; Yun-Nan Chang (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Design of a 2D graphics front-end rendering processor. - Yun-Nan Chang; Ting-Chi Tong (ASAP, 2014)

An OpenGL ES 2.0 3D graphics SoC with versatile HW/SW development support. - Hsu-Kang Dow; Ching-Hua Huang; Chun-Hung Lai; Kai-Hsiang Tsao; Sheng-Chih Tseng; Kun-Yi Wu; Ting-Hsuan Wu; Ho-Chun Yang; Da-Jing Zhang-Jian; Yun-Nan Chang; Steve Haga; Shen-Fu Hsiao; et al. (VLSI-DAT, 2015)

An Efficient Curve-Scanline Intersection Locator Design for 2D Graphics Rendering. - Yun-Nan Chang; Ting-Chi Tong (J. Signal Process. Syst., 2015)

Design of an area-efficient partial-sum architecture for polar decoders based on new matrix generator. - Yun-Nan Chang (NEWCAS, 2016)

A fast ray tracing scheme for dynamic scenes. - Yun-Nan Chang; Chin-Lun Yang (CoDIT, 2017)

Design of A Bit-Serial Artificial Neuron VLSI Architecture with Early Termination. - Yun-Nan Chang; Guan-Jhen Chen (ICEIC, 2019)

Scaling Bit-Flexible Neural Networks. - Yun-Nan Chang; Yu-Tang Tin (ISOCC, 2019)

Design of Low-cost IOU Circuit for Post-processing of Object Detection. - Yun-Nan Chang (GCCE, 2023)