VST: A virtual stress testing framework for discovering bugs in SSD flash-translation layers. - Ren-Shuo Liu; Yun-Sheng Chang; Chih-Wen Hung (ICCAD, 2017)

A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors. - Wei-Hao Chen; Kai-Xiang Li; Wei-Yu Lin; Kuo-Hsiang Hsu; Pin-Yi Li; Cheng-Han Yang; Cheng-Xin Xue; En-Yu Yang; Yen-Kai Chen; Yun-Sheng Chang; Tzu-Hsiang Hsu; Ya-Chin King; et al. (ISSCC, 2018)

Physically Tightly Coupled, Logically Loosely Coupled, Near-Memory BNN Accelerator (PTLL-BNN). - Yun-Chen Lo; Yu-Chun Kuo; Yun-Sheng Chang; Jian-Hao Huang; Jun-Shen Wu; Wen-Chien Ting; Tai-Hsing Wen; Ren-Shuo Liu (ESSCIRC, 2019)

OPTR: Order-Preserving Translation and Recovery Design for SSDs with a Standard Block Device Interface. - Yun-Sheng Chang; Ren-Shuo Liu (USENIX ATC, 2019)

Determinizing Crash Behavior with a Verified Snapshot-Consistent Flash Translation Layer. - Yun-Sheng Chang; Yao Hsiao; Tzu-Chi Lin; Che-Wei Tsao; Chun-Feng Wu; Yuan-Hao Chang 001; Hsiang-Shang Ko; Yu-Fang Chen 001 (OSDI, 2020)

Don't Look Back, Look into the Future: Prescient Data Partitioning and Migration for Deterministic Database Systems. - Yu-Shan Lin; Ching Tsai; Tz-Yu Lin; Yun-Sheng Chang; Shan-Hung Wu (SIGMOD Conference, 2021)

Weakly Durable High-Performance Transactions. - Yun-Sheng Chang; Yu-Fang Chen 001; Hsiang-Shang Ko (CoRR, 2021)

Verifying vMVCC, a high-performance transaction library using multi-version concurrency control. - Yun-Sheng Chang; Ralf Jung 002; Upamanyu Sharma; Joseph Tassarotti; M. Frans Kaashoek; Nickolai Zeldovich (OSDI, 2023)

Hovering Flight of Soft-Actuated Insect-Scale Micro Aerial Vehicles using Deep Reinforcement Learning. - Yi-Hsuan Hsiao; Wei-Tung Chen; Yun-Sheng Chang; Pulkit Agrawal 001; YuFeng Chen 003 (RoboSoft, 2025)