A 10∼15b 60MS/s floating-point ADC with digital gain and offset calibration. - Yun-Shiang Shu; Moon-Jung Kyung; Wei-Ming Lee; Bang-Sup Song; Bedabrata Pain (CICC, 2008)

A 65nm CMOS CT ΔΣ Modulator with 81dB DR and 8MHz BW Auto-Tuned by Pulse Injection. - Yun-Shiang Shu; Bang-Sup Song; Kantilal Bacrania (ISSCC, 2008)

A 15-bit Linear 20-MS/s Pipelined ADC Digitally Calibrated With Signal-Dependent Dithering. - Yun-Shiang Shu; Bang-Sup Song (IEEE J. Solid State Circuits, 2008)

A self-calibrated 2-1-1 cascaded continuous-time ΔΣ modulator. - Junpei Kamiishi; Yun-Shiang Shu; Koji Tomioka; Koichi Hamashita; Bang-Sup Song (CICC, 2009)

A 10∼15-bit 60-MS/s Floating-Point ADC With Digital Gain and Offset Calibration. - Yun-Shiang Shu; Moon-Jung Kyung; Wei-Ming Lee; Bang-Sup Song; Bedabrata Pain (IEEE J. Solid State Circuits, 2009)

LMS-Based Noise Leakage Calibration of Cascaded Continuous-Time Delta Sigma Modulators. - Yun-Shiang Shu; Junpei Kamiishi; Koji Tomioka; Koichi Hamashita; Bang-Sup Song (IEEE J. Solid State Circuits, 2010)

A 6b 3GS/s 11mW fully dynamic flash ADC in 40nm CMOS with reduced number of comparators. - Yun-Shiang Shu (VLSIC, 2012)

A 28fJ/conv-step CT ΔΣ modulator with 78dB DR and 18MHz BW in 28nm CMOS using a highly digital multibit quantizer. - Yun-Shiang Shu; Jui-Yuan Tsai; Ping Chen; Tien-Yu Lo; Pao-Cheng Chiu (ISSCC, 2013)

A background calibration technique for fully dynamic flash ADCs. - Yun-Shiang Shu; Jui-Yuan Tsai; Ping Chen; Tien-Yu Lo; Pao-Cheng Chiu (VLSI-DAT, 2013)

A 1V 9pA analog front end with compressed sensing for electrocardiogram monitoring. - Liang-Ting Kuo; Chun-Chih Hou; Meng-Hsuan Wu; Yun-Shiang Shu (A-SSCC, 2015)

27.2 an oversampling SAR ADC with DAC mismatch error shaping achieving 105dB SFDR and 101dB SNDR over 1kHz BW in 55nm CMOS. - Yun-Shiang Shu; Liang-Ting Kuo; Tien-Yu Lo (ISSCC, 2016)

An Oversampling SAR ADC With DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS. - Yun-Shiang Shu; Liang-Ting Kuo; Tien-Yu Lo (IEEE J. Solid State Circuits, 2016)

An 8 × - OSR 25MHz-BW 79.4dB/74dB DR/SNDR CT Δ σ Modulator Using 7b Linearized Segmented DACs with Digital Noise-Coupling-Compensation Filter in 7nm FinFET CMOS. - Tien-Yu Lo; Chan-Hsiang Weng; Hung-Yi Hsieh; Yun-Shiang Shu; Pao-Cheng Chiu (ISSCC, 2019)

An Amplifier-Less Calibration-Free SAR ADC Achieving >100dB SNDR for Multi-Channel ECG Acquisition with 667mVpp Linear Input Range. - Wei-Hsiang Huang; Su-Hao Wu; Zhi-Xin Chen; Yun-Shiang Shu (VLSI Circuits, 2019)

26.1 A 4.5mm2 Multimodal Biosensing SoC for PPG, ECG, BIOZ and GSR Acquisition in Consumer Wearable Devices. - Yun-Shiang Shu; Zhi-Xin Chen; Yu-Hong Lin; Su-Hao Wu; Wei-Hsiang Huang; Albert Yen-Chih Chiou; Chang-Yang Huang; Hung-Yi Hsieh; Fan-Wei Liao; Teng-Feng Zou; Ping Chen (ISSCC, 2020)

9.1 A Current-Sensing Front-End Realized by A Continuous-Time Incremental ADC with 12b SAR Quantizer and Reset-Then-Open Resistive DAC Achieving 140dB DR and 8ppm INL at 4kS/s. - Su-Hao Wu; Yun-Shiang Shu; Albert Yen-Chih Chiou; Wei-Hsiang Huang; Zhi-Xin Chen; Hung-Yi Hsieh (ISSCC, 2020)

F2: Pushing the Frontiers in Accuracy for Data Converters and Analog Circuits. - Youngcheol Chae; Yun-Shiang Shu; Jens Anders; Viola Schaffer; Takashi Oshima; Marco Corsi (ISSCC, 2021)

Design Techniques for High Linearity and Dynamic Range Digital to Analog Converters. - Ayman Shabra; Yun-Shiang Shu; Shon-Hang Wen; Kuan-Dar Chen (CICC, 2022)

Introduction of Noise-Shaping SAR ADCs. - Yun-Shiang Shu (VLSI-DAT, 2022)

24.6 A Power- and Area-Efficient 4nm Self-Calibrated 12b/16GS/s Hierarchical Time-Interleaving ADC. - Cheng-En Hsieh; Gabriele Manganaro; Sheng-Hui Liao; Jack Weng; Tsun-Yuan Fan; Alec Chin; Tsung-Chih Hung; Jonathan X. Wu; Chi-Lun Lo; Andy Pan; Ming-Hang Hsieh; Yun-Shiang Shu; et al. (ISSCC, 2025)