A Low-delay Configurable Register for FPGA. - Zhi-Yin Lu; Jia-Feng Liu; Yunbing Pang; Zhengjie Li; Yufan Zhang; Jin-Mei Lai 001; Jian Wang 036 (ASICON, 2019)

Research on Area Modeling Methodology for FPGA Interconnect Circuits. - Yunbing Pang; Jiqing Xu; Zhiyin Lu; Zhengjie Li; Yufan Zhang; Jinmei Lai 001 (ASICON, 2019)

Research on the impact of different benchmark circuits on the representative path in FPGAs. - Jiqing Xu; Zhengjie Li; Yunbing Pang; Jian Wang 036; Gang Qu 001; Jinmei Lai (ASICON, 2019)

Transistor-Level Optimization Methodology for GRM FPGA Interconnect Circuits. - Zhengjie Li; Yuanlong Xiao; Yufan Zhang; Yunbing Pang; Jian Wang 036; Jinmei Lai 001 (FPGA, 2019)

An Automatic Transistor-Level Tool for GRM FPGA Interconnect Circuits Optimization. - Zhengjie Li; Yuanlong Xiao; Yufan Zhang; Yunbing Pang; Chengyu Hu; Jian Wang 036; Jinmei Lai 001 (ACM Great Lakes Symposium on VLSI, 2019)