Digital Noise-Coupling Technique for Delta-Sigma Modulators With Segmented Quantization. - Lin He 003; Yuncheng Zhang; Fang Long; Fengcheng Mei; Mingyuan Yu; Fujiang Lin; Libin Yao; Xicheng Jiang (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A Multibit Delta-Sigma Modulator With Double Noise-Shaped Segmentation. - Lin He 003; Guanglong Zhu; Fang Long; Yuncheng Zhang; Li Wang; Fujiang Lin; Libin Yao; Xicheng Jiang (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A parameter adaptive identification method for a pumped storage hydro unit regulation system model using an improved gravitational search algorithm. - Yanhe Xu; Jianzhong Zhou; Chu Zhang 002; Yuncheng Zhang; Chaoshun Li; Zhongdong Qian (Simul., 2017)

A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique. - Bangan Liu; Huy Cu Ngo; Kengo Nakata; Wei Deng 001; Yuncheng Zhang; Junjun Qiu; Toru Yoshioka; Jun Emmei; Haosheng Zhang; Jian Pang; Aravind Tharayil Narayanan; Dongsheng Yang 002; et al. (CICC, 2018)

Synergetic governing controller design for the hydraulic turbine governing system with complex conduit system. - Jianzhong Zhou; Yuncheng Zhang; Yang Zheng 004; Yanhe Xu (J. Frankl. Inst., 2018)

An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration. - Bangan Liu; Yuncheng Zhang; Junjun Qiu; Wei Deng 001; Zule Xu; Haosheng Zhang; Jian Pang; Yun Wang 008; Rui Wu 001; Teruki Someya; Atsushi Shirane; Kenichi Okada 001 (CICC, 2019)

A 29% PAE 1.5Bit-DSM-Based Polar Transmitter with Spur-Mitigated Injection-Locked PLL. - Yuncheng Zhang; Bangan Liu; Xiaofan Gu; Chun Wang; Kiyoshi Yanagisawa; Junjun Qiu; Yun Wang 008; Jian Pang; Atsushi Shirane; Kenichi Okada 001 (VLSI Circuits, 2020)

A DSM-based Polar Transmitter with 23.8% System Efficiency. - Yuncheng Zhang; Bangan Liu; Xiaofan Gu; Chun Wang; Atsushi Shirane; Kenichi Okada 001 (ASP-DAC, 2021)

A 0.25 mm2 BLE Transmitter with Direct Antenna Interface and 19% System Efficiency Using Duty-Cycled Edge-Timing Calibration. - Zheng Sun 001; Dingxin Xu; Junjun Qiu; Zezheng Liu; Yuncheng Zhang; Hongye Huang; Hanli Liu; Bangan Liu; Zheng Li 021; Jian Pang; Atsushi Shirane; Kenichi Okada 001 (ESSCIRC, 2021)

32.7 A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth. - Junjun Qiu; Zheng Sun 001; Bangan Liu; Wenqian Wang; Dingxin Xu; Hans Herdian; Hongye Huang; Yuncheng Zhang; Yun Wang 008; Atsushi Shirane; Kenichi Okada 001 (ISSCC, 2021)

A Fast-Beam-Switching 28-GHz Phased-Array Transceiver Supporting Cross-Polarization Leakage Self-Cancellation. - Jian Pang; Zheng Li 021; Xueting Luo; Joshua Alvin; Kiyoshi Yanagisawa; Yi Zhang 092; Zixin Chen; Zhongliang Huang; Xiaofan Gu; Weichu Chen; Yun Wang 008; Dongwon You; et al. (VLSI Circuits, 2021)

A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems. - Jian Pang; Zheng Li 021; Xueting Luo; Joshua Alvin; Rattanan Saengchan; Ashbir Aviat Fadila; Kiyoshi Yanagisawa; Yi Zhang 092; Zixin Chen; Zhongliang Huang; Xiaofan Gu; Rui Wu 001; et al. (IEEE J. Solid State Circuits, 2021)

A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth. - Junjun Qiu; Zheng Sun 001; Bangan Liu; Wenqian Wang; Dingxin Xu; Hans Herdian; Hongye Huang; Yuncheng Zhang; Yun Wang 008; Jian Pang; Hanli Liu; Masaya Miyahara; et al. (IEEE J. Solid State Circuits, 2021)

A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration. - Bangan Liu; Yuncheng Zhang; Junjun Qiu; Huy Cu Ngo; Wei Deng 001; Kengo Nakata; Toru Yoshioka; Jun Emmei; Jian Pang; Aravind Tharayil Narayanan; Haosheng Zhang; Teruki Someya; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

NTIRE 2022 Challenge on Efficient Super-Resolution: Methods and Results. - Yawei Li 001; Kai Zhang 008; Radu Timofte; Luc Van Gool; Fangyuan Kong; Mingxi Li; Songwei Liu; Zongcai Du; Ding Liu 001; Chenhui Zhou; Jingyi Chen; Qingrui Han; et al. (CVPR Workshops, 2022)

A low-power digital baseband circuit for GMSK demodulation in sub-GHz application. - Junjun Qiu; Bangan Liu; Yuncheng Zhang; Atsushi Shirane; Kenichi Okada 001 (IEICE Electron. Express, 2022)

A 0.37mm2 Fully-Integrated Wide Dynamic Range Sub-GHz Receiver Front-End without Off-Chip Matching Components. - Yuncheng Zhang; Bangan Liu; Teruki Someya; Rui Wu 001; Junjun Qiu; Atsushi Shirane; Kenichi Okada 001 (IEICE Trans. Electron., 2022)

A Ka-Band SATCOM Transceiver in 65-nm CMOS With High-Linearity TX and Dual-Channel Wide-Dynamic-Range RX for Terrestrial Terminal. - Yun Wang 008; Dongwon You; Xi Fu; Takeshi Nakamura; Ashbir Aviat Fadila; Teruki Someya; Atsuhiro Kawaguchi; Junjun Qiu; Jian Pang; Kiyoshi Yanagisawa; Bangan Liu; Yuncheng Zhang; et al. (IEEE J. Solid State Circuits, 2022)

An Ultrasonic Reverse Time Migration Imaging Method Based on Higher-Order Singular Value Decomposition. - Yuncheng Zhang; Xiang Gao; Jiawei Zhang; Jingpin Jiao (Sensors, 2022)

A 6.5-to-8GHz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7dBc Fractional Spurs with 50MHz Reference. - Dingxin Xu; Yuncheng Zhang; Hongye Huang; Zheng Sun 001; Bangan Liu; Ashbir Aviat Fadila; Junjun Qiu; Zezheng Liu; Wenqian Wang; Yuang Xiong; Waleed Madany; Atsushi Shirane; et al. (CICC, 2023)

A Fully Synthesizable DPLL with Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation Path. - Waleed Madany; Yuncheng Zhang; Ashbir Aviat Fadila; Hongye Huang; Junjun Qiu; Atsushi Shirane; Kenichi Okada 001 (ESSCIRC, 2023)

A 2.95mW/element Ka-band CMOS Phased-Array Receiver Utilizing On-Chip Distributed Radiation Sensors in Low-Earth-Orbit Small Satellite Constellation. - Xi Fu; Dongwon You; Xiaolin Wang; Michihiro Ide; Yuncheng Zhang; Jun Sakamaki; Ashbir Aviat Fadila; Zheng Li 021; Yun Wang 008; Jumpei Sudo; Makoto Higaki; Soichiro Inoue; et al. (ISSCC, 2023)

A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain-Boosted PD and Loop-Gain Calibration. - Junjun Qiu; Wenqian Wang; Zheng Sun 001; Bangan Liu; Yuncheng Zhang; Dingxin Xu; Hongye Huang; Ashbir Aviat Fadila; Zezheng Liu; Waleed Madany; Yuang Xiong; Atsushi Shirane; et al. (ISSCC, 2023)

A Small-Satellite-Mounted 256-Element Ka-Band CMOS Phased-Array Transmitter Achieving 63.8dBm EIRP Under 26.6W Power Consumption Using Single/Dual Circular Polarization Active Coupler. - Dongwon You; Xi Fu; Xiaolin Wang; Yuan Gao; Wenqian Wang; Jun Sakamaki; Hans Herdian; Sena Kato; Michihiro Ide; Yuncheng Zhang; Ashbir Aviat Fadila; Zheng Li 021; et al. (ISSCC, 2023)

A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Transformer Combined FIR FIlter. - Yuncheng Zhang; Zheng Sun 001; Bangan Liu; Junjun Qiu; Dingxin Xu; Yi Zhang 092; Xi Fu; Dongwon You; Hongye Huang; Waleed Madany; Ashbir Aviat Fadila; Zezheng Liu; et al. (VLSI Technology and Circuits, 2023)

A Low-Power 256-Element Ka-Band CMOS Phased-Array Receiver With On-Chip Distributed Radiation Sensors for Small Satellite Constellations. - Xi Fu; Dongwon You; Xiaolin Wang; Yun Wang 008; Carolyn Jill Mayeda; Yuan Gao; Michihiro Ide; Yuncheng Zhang; Jun Sakamaki; Ashbir Aviat Fadila; Zheng Li 021; Jumpei Sudo; et al. (IEEE J. Solid State Circuits, 2023)

24.3 A 236-to-266GHz 4-Element Amplifier-Last Phased-Array Transmitter in 65nm CMOS. - Chun Wang; Hans Herdian; Wenbin Zheng; Chenxin Liu; Jill C. Mayeda; Yuxuan Liu; Olivia Angel Yong; Wenqian Wang; Yuncheng Zhang; Carrel da Gomez; Abanob Shehata; Sena Kato; et al. (ISSCC, 2024)

10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter. - Dingxin Xu; Zezheng Liu; Yifeng Kuai; Hongye Huang; Yuncheng Zhang; Zheng Sun 001; Bangan Liu; Wenqian Wang; Yuang Xiong; Junjun Qiu; Waleed Madany; Yi Zhang 092; et al. (ISSCC, 2024)

A 28GHz 4-Stream Time-Division MIMO Phased-Array Receiver Utilizing Nyquist-Rate Fast Beam Switching for 5G and Beyond. - Yi Zhang 092; Minzhe Tang; Jian Pang; Zheng Li 021; Dongfan Xu; Dingxin Xu; Yuncheng Zhang; Kazuaki Kunihiro; Hiroyuki Sakai 009; Atsushi Shirane; Kenichi Okada 001 (VLSI Technology and Circuits, 2024)

Design of Synthesizable Digital Phase Locked Loops. - Yuncheng Zhang; Kenichi Okada 001 (IPSJ Trans. Syst. LSI Des. Methodol., 2024)

A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Hybrid FIR Filter. - Yuncheng Zhang; Zheng Sun 001; Bangan Liu; Junjun Qiu; Dingxin Xu; Yi Zhang 092; Xi Fu; Dongwon You; Hongye Huang; Waleed Madany; Ashbir Aviat Fadila; Zezheng Liu; et al. (IEEE J. Solid State Circuits, 2024)

A 6.65-to-7.75GHz Fractional-N Digital PLL with Analog Pre-Distortion DTC Implementing 2nd/3rd-Order Calibration and Achieving -65.7dBc Fractional Spur and 154fs Integrated Jitter. - Daxu Zhang; Dingxin Xu; Hongye Huang; Waleed Madany; Zezheng Liu; Wenqian Wang; Yuang Xiong; Ashbir Aviat Fadila; Duo Li; Yuncheng Zhang; Atsushi Shirane; Kenichi Okada 001 (CICC, 2025)

5.6 A Power-Efficient CORDIC-Less Digital Polar Transmitter Using 1b DSM-Based PA Supporting 256-QAM. - Yuncheng Zhang; Zezheng Liu; Duo Li; Minzhe Tang; Yi Zhang 092; Hongye Huang; Dingxin Xu; Waleed Madany; Ashbir Aviat Fadila; Wenqian Wang; Yuang Xiong; Daxu Zhang; et al. (ISSCC, 2025)

NLJM: A Simplified Jitter Model of Digital Standard Cells for Rapid Automatic Design of Frequency Synthesizers. - Hongye Huang; Ashbir Aviat Fadila; Dingxin Xu; Waleed Madany; Wenqian Wang; Zezheng Liu; Yuang Xiong; Tianshi Hu; Bangan Liu; Yuncheng Zhang; Atsushi Shirane; Kenichi Okada 001 (IEEE Access, 2025)

A 0.8-1.4-GHz Synthesizable DPLL Using a Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation. - Waleed Madany; Yuncheng Zhang; Ashbir Aviat Fadila; Hongye Huang; Junjun Qiu; Jill C. Mayeda; Atsushi Shirane; Kenichi Okada 001 (IEEE Access, 2025)

An Interface Reconstruction Method Based on the Physics-Informed Neural Network: Application to Ultrasonic Array Imaging. - Xiang Gao; Yuncheng Zhang; Yanxun Xiang; Peng Li 057; Xiucheng Liu (IEEE Trans. Instrum. Meas., 2025)

Adaptive Spatial Wavenumber Estimation: A Computationally Efficient Laser Scanning Ultrasonic Guided Wavefield Imaging for Depth-Resolved Inspection. - Xuan Li; Lishuai Liu; Yuncheng Zhang; Jiang Lu; Yanxun Xiang (IEEE Trans. Instrum. Meas., 2025)

A 6.5-to-8-GHz Cascaded Dual-Fractional-N Digital PLL Achieving -52.79-dBc Fractional Spur With 50-MHz Reference. - Dingxin Xu; Yuncheng Zhang; Hongye Huang; Zheng Sun 001; Bangan Liu; Ashbir Aviat Fadila; Junjun Qiu; Zezheng Liu; Wenqian Wang; Yuang Xiong; Waleed Madany; Atsushi Shirane; et al. (IEEE J. Solid State Circuits, 2025)

A DPD/Dither-Free DPLL Based on a Cascaded Fractional Divider and Pseudo-Differential DTCs Achieving a - 62.1-dBc Fractional Spur. - Dingxin Xu; Zezheng Liu; Yifeng Kuai; Hongye Huang; Yuncheng Zhang; Zheng Sun 001; Bangan Liu; Wenqian Wang; Yuang Xiong; Junjun Qiu; Waleed Madany; Yi Zhang 092; et al. (IEEE J. Solid State Circuits, 2025)