An Improved Approach for AlternativeWires Identi.cation. - Yung-Chih Chen; Chun-Yao Wang (ICCD, 2005)

Language-Based High Level Transaction Extraction on On-chip Buses. - Yi-Le Huang; Chun-Yao Wang; Richard Yeh; Shih-Chieh Chang; Yung-Chih Chen (ISQED, 2006)

Improving Bluetooth EDR Data Throughput Using FEC and Interleaving. - Ling-Jyh Chen; Tony Sun; Yung-Chih Chen (MSN, 2006)

A hybrid routing approach for opportunistic networks. - Ling-Jyh Chen; Chen-Hung Yu; Tony Sun; Yung-Chih Chen; Hao-Hua Chu (CHANTS@SIGCOMM, 2006)

Finding Self-Similarities in Opportunistic People Networks. - Ling-Jyh Chen; Yung-Chih Chen; Tony Sun; Paruvelli Sreedevi; Kuan-Ta Chen; Chen-Hung Yu; Hao-Hua Chu (INFOCOM, 2007)

A Novel Mobility Model from a Heterogeneous Military MANET Trace. - Xiaofeng Lu; Yung-Chih Chen; Ian X. Y. Leung; Zhang Xiong 001; Pietro Liò (ADHOC-NOW, 2008)

A Statistic-Based Approach to Testability Analysis. - Chuang-Chi Chiou; Chun-Yao Wang; Yung-Chih Chen (ISQED, 2008)

An Implicit Approach to Minimizing Range-Equivalent Circuits. - Yung-Chih Chen; Chun-Yao Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Novel Probabilistic Combinational Equivalence Checking. - Shih-Chieh Wu; Chun-Yao Wang; Yung-Chih Chen (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Enhancing SAT-based sequential depth computation by pruning search space. - Yung-Chih Chen; Chun-Yao Wang (ACM Great Lakes Symposium on VLSI, 2009)

Fast detection of node mergers using logic implications. - Yung-Chih Chen; Chun-Yao Wang (ICCAD, 2009)

An efficient approach to sip design integration. - Meng-Syue Chan; Chun-Yao Wang; Yung-Chih Chen (ISQED, 2009)

A novel ACO-based pattern generation for peak power estimation in VLSI circuits. - Yi-Ling Liu; Chun-Yao Wang; Yung-Chih Chen; Ya-Hsin Chang (ISQED, 2009)

Dependent-Latch Identification in Reachable State Space. - Chen-Hsuan Lin 001; Chun-Yao Wang; Yung-Chih Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Node addition and removal in the presence of don't cares. - Yung-Chih Chen; Chun-Yao Wang (DAC, 2010)

Group detection in mobility traces. - Yung-Chih Chen; Elisha J. Rosensweig; Jim Kurose; Donald F. Towsley (IWCMC, 2010)

An Analytical Study of People Mobility in Opportunistic Networks. - Ling-Jyh Chen; Yung-Chih Chen (J. Inf. Sci. Eng., 2010)

Fast Node Merging With Don't Cares Using Logic Implications. - Yung-Chih Chen; Chun-Yao Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Automated mapping for reconfigurable single-electron transistor arrays. - Yung-Chih Chen; Soumya Eachempati; Chun-Yao Wang; Suman Datta; Yuan Xie 001; Vijaykrishnan Narayanan (DAC, 2011)

A recursive SVD-based self-constructing rule generation for neuro-fuzzy system modeling. - Chen-Sen Ouyang; Chih-Chung Wang; Yung-Chih Chen (ICMLC, 2011)

A simple queueing network model of mobility in a campus wireless network. - Yung-Chih Chen; Jim Kurose; Don Towsley (S3@MobiCom, 2011)

Ultrasonography Image Analysis for Detection and Classification of Chronic Kidney Disease. - Chih-Yin Ho; Tun-Wen Pai; Yuan-Chi Peng; Chien-Hung Lee; Yung-Chih Chen; Yang-Ting Chen; Kuo-Su Chen (CISIS, 2012)

A probabilistic analysis method for functional qualification under Mutation Analysis. - Hsiu-Yi Lin; Chun-Yao Wang; Shih-Chieh Chang; Yung-Chih Chen; Hsuan-Ming Chou; Ching-Yi Huang; Yen-Chi Yang; Chun-Chien Shen (DATE, 2012)

A mixed queueing network model of mobility in a campus wireless network. - Yung-Chih Chen; Jim Kurose; Don Towsley (INFOCOM, 2012)

Logic Restructuring Using Node Addition and Removal. - Yung-Chih Chen; Chun-Yao Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

On reconfigurable single-electron transistor arrays synthesis using reordering techniques. - Chang-En Chiang; Li-Fu Tang; Chun-Yao Wang; Ching-Yi Huang; Yung-Chih Chen; Suman Datta; Vijaykrishnan Narayanan (DATE, 2013)

Sensitization criterion for threshold logic circuits and its application. - Chen-Kuan Tsai; Chun-Yao Wang; Ching-Yi Huang; Yung-Chih Chen (ICCAD, 2013)

A measurement-based study of MultiPath TCP performance over wireless networks. - Yung-Chih Chen; Yeon-Sup Lim; Richard J. Gibbens; Erich M. Nahum; Ramin Khalili; Don Towsley (Internet Measurement Conference, 2013)

Pattern generation for Mutation Analysis using Genetic Algorithms. - Yen-Chi Yang; Chun-Yao Wang; Ching-Yi Huang; Yung-Chih Chen (ISCAS, 2013)

Multi-Source Multi-Path HTTP (mHTTP): A Proposal. - Juhoon Kim; Ramin Khalili; Anja Feldmann; Yung-Chih Chen; Don Towsley (CoRR, 2013)

A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays. - Yung-Chih Chen; Soumya Eachempati; Chun-Yao Wang; Suman Datta; Yuan Xie 001; Vijaykrishnan Narayanan (ACM J. Emerg. Technol. Comput. Syst., 2013)

Verification of Reconfigurable Binary Decision Diagram-Based Single-Electron Transistor Arrays. - Yung-Chih Chen; Chun-Yao Wang; Ching-Yi Huang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

MSPlayer: Multi-Source and multi-Path LeverAged YoutubER. - Yung-Chih Chen; Don Towsley; Ramin Khalili (CoNEXT, 2014)

Rewiring for threshold logic circuit minimization. - Chia-Chun Lin; Chun-Yao Wang; Yung-Chih Chen; Ching-Yi Huang (DATE, 2014)

Width minimization in the Single-Electron Transistor array synthesis. - Chian-Wei Liu; Chang-En Chiang; Ching-Yi Huang; Chun-Yao Wang; Yung-Chih Chen; Suman Datta; Vijaykrishnan Narayanan (DATE, 2014)

Stage diagnosis for Chronic Kidney Disease based on ultrasonography. - Chi-Jim Chen; Tun-Wen Pai; Hamido Fujita; Chien-Hung Lee; Yang-Ting Chen; Kuo-Su Chen; Yung-Chih Chen (FSKD, 2014)

Cross-layer path management in multi-path transport protocol for mobile devices. - Yeon-Sup Lim; Yung-Chih Chen; Erich M. Nahum; Don Towsley; Kang-Won Lee (INFOCOM, 2014)

On bufferbloat and delay analysis of multipath TCP in wireless networks. - Yung-Chih Chen; Don Towsley (Networking, 2014)

How green is multipath TCP for mobile devices? - Yeon-Sup Lim; Yung-Chih Chen; Erich M. Nahum; Don Towsley; Richard J. Gibbens (AllThingsCellular@SIGCOMM, 2014)

Multi-source multipath HTTP (mHTTP): a proposal. - Juhoon Kim; Yung-Chih Chen; Ramin Khalili; Don Towsley; Anja Feldmann (SIGMETRICS, 2014)

SAT-based complete logic implication with application to logic optimization. - Yung-Chih Chen; Kung-Ming Ji (VLSI-DAT, 2014)

Improving Energy Efficiency of MPTCP for Mobile Devices. - Yeon-Sup Lim; Yung-Chih Chen; Erich M. Nahum; Don Towsley; Richard J. Gibbens (CoRR, 2014)

Hybrid LUT and SOP Reconfigurable Architecture. - Po-Yang Hsu; Yung-Chih Chen; Yi-Yu Liu (J. Inf. Sci. Eng., 2014)

A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays. - Ching-Yi Huang; Chian-Wei Liu; Chun-Yao Wang; Yung-Chih Chen; Suman Datta; Vijaykrishnan Narayanan (ASP-DAC, 2015)

Design, implementation, and evaluation of energy-aware multi-path TCP. - Yeon-Sup Lim; Yung-Chih Chen; Erich M. Nahum; Don Towsley; Richard J. Gibbens; Emmanuel Cecchet (CoNEXT, 2015)

Using structural relations for checking combinationality of cyclic circuits. - Wan-Chen Weng; Yung-Chih Chen; Jui-Hung Chen; Ching-Yi Huang; Chun-Yao Wang (DATE, 2015)

Measurement of body joint angles for physical therapy based on mean shift tracking using two low cost Kinect images. - Yung-Chih Chen; H. J. Lee; K. H. Lin (EMBC, 2015)

Synthesis and verification of cyclic combinational circuits. - Jui-Hung Chen; Yung-Chih Chen; Wan-Chen Weng; Ching-Yi Huang; Chun-Yao Wang (SoCC, 2015)

Correctness Analysis and Power Optimization for Probabilistic Boolean Circuits. - Ching-Yi Huang; Zheng-Shan Yu; Yung-Chun Hu; Tung-Chen Tsou; Chun-Yao Wang; Yung-Chih Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Synthesis for Width Minimization in the Single-Electron Transistor Array. - Chian-Wei Liu; Chang-En Chiang; Ching-Yi Huang; Yung-Chih Chen; Chun-Yao Wang; Suman Datta; Vijaykrishnan Narayanan (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Fast synthesis of threshold logic networks with optimization. - Yung-Chih Chen; Runyi Wang; Yan-Ping Chang (ASP-DAC, 2016)

MajorSat: A SAT solver to majority logic. - Yu-Min Chou; Yung-Chih Chen; Chun-Yao Wang; Ching-Yi Huang (ASP-DAC, 2016)

MSPlayer: Multi-Source and Multi-Path Video Streaming. - Yung-Chih Chen; Don Towsley; Ramin Khalili (IEEE J. Sel. Areas Commun., 2016)

An Efficient Interpolation-Based Projected Sum of Product Decomposition via Genetic Algorithm. - Tai-Lin Chen; Chun-Yao Wang; Ching-Yi Huang; Yung-Chih Chen (J. Multiple Valued Log. Soft Comput., 2016)

Minimization of Number of Neurons in Voronoi Diagram-Based Artificial Neural Networks. - Chen-Yu Lin; Yung-Chih Chen; Chun-Yao Wang; Ching-Yi Huang; Chiou-Ting Hsu (IEEE Trans. Multi Scale Comput. Syst., 2016)

Area-Aware Decomposition for Single-Electron Transistor Arrays. - Ching-Hsuan Ho; Yung-Chih Chen; Chun-Yao Wang; Ching-Yi Huang; Suman Datta; Vijaykrishnan Narayanan (ACM Trans. Design Autom. Electr. Syst., 2016)

Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays. - Ching-Yi Huang; Yun-Jui Li; Chian-Wei Liu; Chun-Yao Wang; Yung-Chih Chen; Suman Datta; Vijaykrishnan Narayanan (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Majority logic circuits optimisation by node merging. - Chun-Che Chung; Yung-Chih Chen; Chun-Yao Wang; Chia-Cheng Wu (ASP-DAC, 2017)

Tree-Based Logic Encryption for Resisting SAT Attack. - Yung-Chih Chen (ATS, 2017)

In&Out: Restructuring for threshold logic network optimization. - Chia-Chun Lin; Chiao-Wei Huang; Chun-Yao Wang; Yung-Chih Chen (ISQED, 2017)

Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays. - Yun-Jui Li; Ching-Yi Huang; Chia-Cheng Wu; Yung-Chih Chen; Chun-Yao Wang; Suman Datta; Vijaykrishnan Narayanan (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Efficient synthesis of approximate threshold logic circuits with an error rate guarantee. - Yung-An Lai; Chia-Chun Lin; Chia-Cheng Wu; Yung-Chih Chen; Chun-Yao Wang (DATE, 2018)

Logic optimization with considering boolean relations. - Tung-Yuan Lee; Chia-Cheng Wu; Chia-Chun Lin; Yung-Chih Chen; Chun-Yao Wang (DATE, 2018)

A Hybrid Approach to Equivalent Fault Identification for Verification Environment Qualification. - Chia-Cheng Wu; Tung-Yuan Lee; Yung-An Lai; Hsin-Pei Wang; De-Xuan Ji; Yan-Ping Chang; Teng-Chia Wang; Chin-Heng Liu; Chun-Yao Wang; Yung-Chih Chen (ACM Great Lakes Symposium on VLSI, 2018)

Using range-equivalent circuits for facilitating bounded sequential equivalence checking. - Yung-Chih Chen; Wei-An Ji; Chih-Chung Wang; Ching-Yi Huang; Chia-Cheng Wu; Chia-Chun Lin; Chun-Yao Wang (VLSI-DAT, 2018)

Optimization of threshold logic networks with ODC-based node merging. - Fu-Lian Wong; Li-Cheng Zheng; Yung-Chih Chen (VLSI-DAT, 2018)

Enhancements to SAT Attack: Speedup and Breaking Cyclic Logic Encryption. - Yung-Chih Chen (ACM Trans. Design Autom. Electr. Syst., 2018)

Contactless Testing for Prebond Interposers. - Kai-Hsiang Hsu; Yung-Chih Chen; You-Luen Lee; Shih-Chieh Chang (IEEE Trans. Very Large Scale Integr. Syst., 2018)

On Synthesizing Memristor-Based Logic Circuits With Minimal Operational Pulses. - Hsin-Pei Wang; Chia-Chun Lin; Chia-Cheng Wu; Yung-Chih Chen; Chun-Yao Wang (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A Smart Single-Sensor Device for Instantaneously Monitoring Lower Limb Exercises. - Yan-Ping Chang; Teng-Chia Wang; Yun-Ju Lee; Chia-Chun Lin; Yung-Chih Chen; Chun-Yao Wang (SoCC, 2019)

A Glitch Key-Gate for Logic Locking. - De-Xuan Ji; Hsiao-Yu Chiang; Chia-Chun Lin; Chia-Cheng Wu; Yung-Chih Chen; Chun-Yao Wang (SoCC, 2019)

Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments. - Chin-Heng Liu; Chia-Chun Lin; Yung-Chih Chen; Chia-Cheng Wu; Chun-Yao Wang; Shigeru Yamashita (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Optimization of Threshold Logic Networks with Node Merging and Wire Replacement. - Yung-Chih Chen; Li-Cheng Zheng; Fu-Lian Wong (ACM Trans. Design Autom. Electr. Syst., 2019)

Don't-Care-Based Node Minimization for Threshold Logic Networks. - Yung-Chih Chen; Hao-Ju Chang; Li-Cheng Zheng (DAC, 2020)

A Convolutional Result Sharing Approach for Binarized Neural Network Inference. - Ya-Chun Chang; Chia-Chun Lin; Yi-Ting Lin; Yung-Chih Chen; Chun-Yao Wang (DATE, 2020)

Accuracy Tolerant Neural Networks Under Aggressive Power Optimization. - Xiang-Xiu Wu; Yi-Wen Hung; Yung-Chih Chen; Shih-Chieh Chang (DATE, 2020)

Rehabilitation System for Limbs using IMUs. - Chun-Jui Chen; Yi-Ting Lin; Chia-Chun Lin; Yung-Chih Chen; Yun-Ju Lee; Chun-Yao Wang (ISQED, 2020)

IMU-based Smart Knee Pad for Walking Distance and Stride Count Measurement. - Teng-Chia Wang; Yan-Ping Chang; Chun-Jui Chen; Yun-Ju Lee; Chia-Chun Lin; Yung-Chih Chen; Chun-Yao Wang (ISQED, 2020)

A Dynamic Expansion Order Algorithm for the SAT-based Minimization. - Chia-Chun Lin; Kit Seng Tam; Chana-Cheng Ko; Hsin-Ping Yen; Shenz-Hsiu Wei; Yung-Chih Chen; Chun-Yao Wang (SoCC, 2020)

Prediction of chronic kidney disease stages by renal ultrasound imaging. - Chi-Jim Chen; Tun-Wen Pai; Hui-Huang Hsu; Chien-Hung Lee; Kuo-Su Chen; Yung-Chih Chen (Enterp. Inf. Syst., 2020)

SMARTLock: SAT Attack and Removal Attack-Resistant Tree-Based Logic Locking. - Yung-Chih Chen (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020)

LOOPLock: Logic Optimization-Based Cyclic Logic Locking. - Hsiao-Yu Chiang; Yung-Chih Chen; De-Xuan Ji; Xiang-Min Yang; Chia-Chun Lin; Chun-Yao Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

A New Necessary Condition for Threshold Function Identification. - Chia-Chun Lin; Chin-Heng Liu; Yung-Chih Chen; Chun-Yao Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

A General Equivalence Checking Framework for Multivalued Logic. - Chia-Chun Lin; Hsin-Ping Yen; Sheng-Hsiu Wei; Pei-Pei Chen; Yung-Chih Chen; Chun-Yao Wang (ASP-DAC, 2021)

An Efficient Approximate Node Merging with an Error Rate Guarantee. - Kit Seng Tam; Chia-Chun Lin; Yung-Chih Chen; Chun-Yao Wang (ASP-DAC, 2021)

1st-Order to 2nd-Order Threshold Logic Gate Transformation with an Enhanced ILP-based Identification Method. - Li-Cheng Zheng; Hao-Ju Chang; Yung-Chih Chen; Jing-Yang Jou (ASP-DAC, 2021)

Towards Deep Learning-Based Sarcopenia Screening with Body Joint Composition Analysis. - Yung-Chih Chen; Jun-Wei Hsieh; Yao-Hong Yang; Chien-Hung Lee; Pei-Yi Yu; Ping-Yang Chen; Arpita Samanta Santa (ICIP, 2021)

On Synthesizing Memristor-Based Logic Circuits in Area-Constrained Crossbar Arrays. - Hsin-Tsung Lee; Chia-Chun Lin; Yung-Chih Chen; Chun-Yao Wang (ISQED, 2021)

On Reduction of Computations for Threshold Function Identification. - Wen-Chih Hsu; Chia-Chun Lin; Yi-Ting Li; Yung-Chih Chen; Chun-Yao Wang (SoCC, 2021)

Cluster Tool Performance Analysis using Graph Database. - Shiuan-Hau Huang; Hsin-Ping Yen; Yan-Hsiu Liu; Kuang-Hsien Tseng; Ji-Fu Kung; Chia-Chun Lin; Yi-Ting Li; Yung-Chih Chen; Chun-Yao Wang (SoCC, 2021)

An IMU-aided Fitness System. - Yi-Ting Lin; Chun-Jui Chen; Pei-Yi Kuo; Si-Huei Lee; Chia-Chun Lin; Yun-Ju Lee; Yi-Ting Li; Yung-Chih Chen; Chun-Yao Wang (SoCC, 2021)

Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model. - Chia-Cheng Wu; Yi-Hsiang Hu; Chia-Chun Lin; Yung-Chih Chen; Juinn-Dar Huang; Chun-Yao Wang (ACM J. Emerg. Technol. Comput. Syst., 2021)

Dynamic Workload Allocation for Edge Computing. - Yi-Wen Hung; Yung-Chih Chen; Chi Lo; Austin Go So; Shih-Chieh Chang (IEEE Trans. Very Large Scale Integr. Syst., 2021)

An Approach to Unlocking Cyclic Logic Locking: LOOPLock 2.0. - Pei-Pei Chen; Xiang-Min Yang; Yi-Ting Li; Yung-Chih Chen; Chun-Yao Wang (ICCAD, 2022)

Majority Logic Circuit Minimization Using Node Addition and Removal. - Chang-Cheng Ko; Chia-Chun Lin; Yung-Chih Chen; Chun-Yao Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Don't Care Computation and De Morgan Transformation for Threshold Logic Network Optimization. - Chia-Chun Lin; Ciao-Syun Lin; You-Hsuen Tsai; Yung-Chih Chen; Chun-Yao Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A Don't-Care-Based Approach to Reducing the Multiplicative Complexity in Logic Networks. - Hsiao-Lun Liu; Yi-Ting Li; Yung-Chih Chen; Chun-Yao Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

LOOPLock 2.0: An Enhanced Cyclic Logic Locking Approach. - Xiang-Min Yang; Pei-Pei Chen; Hsiao-Yu Chiang; Chia-Chun Lin; Yung-Chih Chen; Chun-Yao Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A High Voltage Driving Chiplet in Standard 0.18-μm CMOS for Micro-Pixelated LED Displays Integrated With LTPS TFTs. - Hsu-Chi Lee; Yun-Chih Lu; Yu-Chen Lin; Wei-Lin Lai; Hsiang-Yuan Hsieh; Boy-Yiing Jaw; Chin-Tang Chuang; Yung-Chih Chen; Yi-Jan Emery Chen (IEEE Trans. Circuits Syst. Video Technol., 2022)

Optimization of Reversible Logic Networks with Gate Sharing. - Yung-Chih Chen; Feng-Jie Chao (ASP-DAC, 2023)

Approximate Logic Synthesis by Genetic Algorithm with an Error Rate Guarantee. - Chun-Ting Lee; Yi-Ting Li; Yung-Chih Chen; Chun-Yao Wang (ASP-DAC, 2023)

A Robust Approach to Detecting Non-Equivalent Quantum Circuits Using Specially Designed Stimuli. - Hsiao-Lun Liu; Yi-Ting Li; Yung-Chih Chen; Chun-Yao Wang (ASP-DAC, 2023)

Expanding In-Cone Obfuscated Tree for Anti SAT Attack. - RuiJie Wang; Li-Nung Hsu; Yung-Chih Chen; TingTing Hwang (DATE, 2023)

An Effective and Efficient Heuristic for Rational-Weight Threshold Logic Gate Identification. - Ting-Yu Yeh; Yueh Cho; Yung-Chih Chen (DATE, 2023)

A Flexible Cluster Tool Simulation Framework with Wafer Batch Dispatching Time Recommendation. - Hsin-Ping Yen; Shiuan-Hau Huang; Yan-Hsiu Liu; Kuang-Hsien Tseng; Ji-Fu Kung; Yi-Ting Li; Yung-Chih Chen; Chun-Yao Wang (ISQED, 2023)

Don't-Care-Based Logic Optimization for Threshold Logic. - Yung-Chih Chen; Li-Cheng Zheng; Hao-Ju Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A Constructive Approach for Threshold Function Identification. - Meng-Jing Li; Yu-Chuan Yen; Yi-Ting Li; Yung-Chih Chen; Chun-Yao Wang (ACM Trans. Design Autom. Electr. Syst., 2023)

LOOPLock 3.0: A Robust Cyclic Logic Locking Approach. - Pei-Pei Chen; Xiang-Min Yang; Yu-Cheng He; Yung-Chih Chen; Yi-Ting Li; Chun-Yao Wang (ASPDAC, 2024)

A Hybrid Approach to Reverse Engineering on Combinational Circuits. - Wuqian Tang; Yi-Ting Li; Kai-Po Hsu; Kuan-Ling Chou; You-Cheng Lin; Chia-Feng Chien; Tzu-Li Hsu; Yung-Chih Chen; Ting-Chi Wang; Shih-Chieh Chang; TingTing Hwang; Chun-Yao Wang (DATE, 2024)

IR drop Prediction Based on Machine Learning and Pattern Reduction. - Yong-Fong Chang; Yung-Chih Chen; Yu-Chen Cheng; Shu-Hong Lin; Che-Hsu Lin; Chun-Yuan Chen; Yu-Hsuan Chen; Yu-Che Lee; Jia-Wei Lin; Hsun-Wei Pao; Shih-Chieh Chang; Yi-Ting Li; et al. (ACM Great Lakes Symposium on VLSI, 2024)

On Construction of Trajectory of Boxer's Punch using a single IMU. - Yu-Cheng Lee; Kai-Po Hsu; Yun-Ju Lee; Yi-Ting Li; Wuqian Tang; Yung-Chih Chen; Wen-Hsin Chiu; Chun-Yao Wang (ISPACS, 2024)

Model Reduction Using a Hybrid Approach of Genetic Algorithm and Rule-based Method. - Wuqian Tang; Chuan-Shun Huang; Yung-Chih Chen; Yi-Ting Li; Shih-Chieh Chang; Chun-Yao Wang (SOCC, 2024)

9-Input Threshold Function Identification Using a New Necessary Condition of Threshold Function. - Yu-Chuan Yen; Meng-Jing Li; Yi-Ting Li; Yung-Chih Chen; Ihao Chen; Chun-Yao Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Dynamic IR-Drop Prediction Through a Multi-Task U-Net with Package Effect Consideration. - Yu-Hsuan Chen; Yu-Chen Cheng; Yong-Fong Chang; Yu-Che Lee; Jia-Wei Lin; Hsun-Wei Pao; Peng-Wen Chen; Po-Yu Chen; Hao-Yun Chen; Yung-Chih Chen; Chun-Yao Wang; Shih-Chieh Chang (DATE, 2025)

CNN Model Optimization Using a Hybrid Approach of Genetic Algorithm-based Pruning and Retraining with Knowledge Distillation. - Kuan-Ling Chou; Cheng-Lung Wang; Yung-Chih Chen; Wuqian Tang; Yi-Ting Li; Shih-Chieh Chang; Chun-Yao Wang (ACM Great Lakes Symposium on VLSI, 2025)

IMU-Based Motion Trajectory Reconstruction and Recognition with Dynamic Calibration on Embedded System Platform. - Kai-Po Hsu; Tsung-Han Lai; Yi-Ting Li; Wuqian Tang; Yun-Ju Lee; Yung-Chih Chen; Wen-Hsin Chiu; Chun-Yao Wang (ISQED, 2025)