Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events. - Chih-Ting Yeh; Yung-Chih Liang; Ming-Dou Ker (ISCAS, 2011)

A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process. - Wei-Bin Yang; Chao-Cheng Liao; Yung-Chih Liang (Microelectron. J., 2011)