An optimal transistor-chaining algorithm for CMOS cell layout. - Chi-Yi Hwang; Yung-Ching Hsieh; Youn-Long Lin; Yu-Chin Hsu (ICCAD, 1989)

LiB: A Cell Layout Generator. - Yung-Ching Hsieh; Chi-Yi Hwang; Youn-Long Lin; Yu-Chin Hsu (DAC, 1990)

An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation. - Chi-Yi Hwang; Yung-Ching Hsieh; Youn-Long Lin; Yu-Chin Hsu (DAC, 1991)

LiB: a CMOS cell compiler. - Yung-Ching Hsieh; Chi-Yi Hwang; Youn-Long Lin; Yu-Chin Hsu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis. - Chi-Yi Hwang; Yung-Ching Hsieh; Youn-Long Lin; Yu-Chin Hsu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache. - Tah-Kang Joseph Ting; Gyh-Bin Wang; Ming-Hung Wang; Chun-Peng Wu; Chun-Kai Wang; Chun-Wei Lo; Li-Chin Tien; Der-Min Yuan; Yung-Ching Hsieh; Jenn-Shiang Lai; Wen-Pin Hsu; Chien-Chih Huang; et al. (ISSCC, 2017)