BDD decomposition for mixed CMOS/PTL logic circuit synthesis. - Yen-Tai Lai; Yung-Chuan Jiang; Hong-Ming Chu (ISCAS (6), 2005)

Temporal Partitioning Data Flow Graphs for Dynamically Reconfigurable Computing. - Yung-Chuan Jiang; Jhing-Fa Wang (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Reduced Communication Costs via Network Flow and Scheduling for Partitions of Dynamically Reconfigurable FPGAs. - Yung-Chuan Jiang; Jhing-Fa Wang (J. Inf. Sci. Eng., 2010)

Computation Aware Scheme for Visual Signal Processing. - Anand Paul 001; Yung-Chuan Jiang; Jhing-Fa Wang (J. Softw., 2010)

Parallel Reconfigurable Computing-Based Mapping Algorithm for Motion Estimation in Advanced Video Coding. - Anand Paul 001; Yung-Chuan Jiang; Jhing-Fa Wang; Jar-Ferr Yang (ACM Trans. Embed. Comput. Syst., 2012)