Just-Enough Strategy for Accurate Clock Jitter Measurement Using A Cyclic Time-to-Digital Converter. - Yung-Chuan Su; Shi-Yu Huang (ISOCC, 2022)

Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization. - Yung-Chuan Su; Shi-Yu Huang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A Process-Adaptive Cell-Based Cyclic Time-to-Digital Converter Using One-Way Varactor Cells. - Yung-Chuan Su; Shi-Yu Huang (IEEE Trans. Very Large Scale Integr. Syst., 2023)