A 1.8V, sub-mW, over 100% locking range, divide-by-3 and 7 complementary-injection-locked 4 GHz frequency divider. - Yung-Chung Lo; Hsien-Pu Chen; José Silva-Martínez; Sebastian Hoyos (CICC, 2009)

A 25 MHz Bandwidth 5th-Order Continuous-Time Low-Pass Sigma-Delta Modulator With 67.7 dB SNDR Using Time-Domain Quantization and Feedback. - Cho-Ying Lu; Marvin Onabajo; Venkata Gadde; Yung-Chung Lo; Hsien-Pu Chen; Vijayaramalingam Periasamy; José Silva-Martínez (IEEE J. Solid State Circuits, 2010)

A Self-Sustained CMOS Microwave Chemical Sensor Using a Frequency Synthesizer. - Ahmed A. Helmy; Hyung-Joon Jeon; Yung-Chung Lo; Andreas J. Larsson; Raghavendra Kulkarni; Jusung Kim; José Silva-Martínez; Kamran Entesari (IEEE J. Solid State Circuits, 2012)

An LC Quadrature VCO Using Capacitive Source Degeneration Coupling to Eliminate Bi-Modal Oscillation. - Haitao Tong; Shanfeng Cheng; Yung-Chung Lo; Aydin I. Karsilayan; José Silva-Martínez (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy. - Hyung-Joon Jeon; Raghavendra Kulkarni; Yung-Chung Lo; Jusung Kim; José Silva-Martínez (IEEE J. Solid State Circuits, 2013)

A 0.6ps jitter 2-16 GHz 130nm CMOS frequency synthesizer for broadband applications. - Yung-Chung Lo; Negar Rashidi; Yin-Huan Hwang; José Silva-Martínez (ISCAS, 2015)