General Modular Multiplication by Block Multiplication and Table Lookup. - Cheng-Wen Wu; Yung-Fa Chou (ISCAS, 1994)

etection of SRAM cell stability by lowering array supply voltage. - Ding-Ming Kwai; Hung-Wen Chang; Hung-Jen Liao; Ching-Hua Chiao; Yung-Fa Chou (Asian Test Symposium, 2000)

Flash Memory Built-In Self-Test Using March-Like Algorithm. - Jen-Chieh Yeh; Chi-Feng Wu; Kuo-Liang Cheng; Yung-Fa Chou; Chih-Tsun Huang; Cheng-Wen Wu (DELTA, 2002)

Defect Oriented Fault Analysis for SRAM. - Rei-Fu Huang; Yung-Fa Chou; Cheng-Wen Wu (Asian Test Symposium, 2003)

FAME: A Fault-Pattern Based Memory Failure Analysis Framework. - Kuo-Liang Cheng; Chih-Wea Wang; Jih-Nung Lee; Yung-Fa Chou; Chih-Tsun Huang; Cheng-Wen Wu (ICCAD, 2003)

Fault Pattern Oriented Defect Diagnosis for Memories. - Chih-Wea Wang; Kuo-Liang Cheng; Jih-Nung Lee; Yung-Fa Chou; Chih-Tsun Huang; Cheng-Wen Wu; Frank Huang; Hong-Tzer Yang (ITC, 2003)

SRAM delay fault modeling and test algorithm development. - Rei-Fu Huang; Yan-Ting Lai; Yung-Fa Chou; Cheng-Wen Wu (ASP-DAC, 2004)

FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal Assignment. - Ding-Ming Kwai; Yung-Fa Chou; Meng-Fan Chang; Su-Meng Yang; Ding-Sheng Chen; Min-Chung Hsu; Yu-Zhen Liao; Shiao-Yi Lin; Yu-Ling Sung; Chia-Hsin Lee; Hsin-Kun Hsu (MTDT, 2006)

SRAM Cell Current in Low Leakage Design. - Ding-Ming Kwai; Ching-Hua Hsiao; Chung-Ping Kuo; Chi-Hsien Chuang; Min-Chung Hsu; Yi-Chun Chen; Yu-Ling Sung; Hsien-Yu Pan; Chia-Hsin Lee; Meng-Fan Chang; Yung-Fa Chou (MTDT, 2006)

Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms. - Jen-Chieh Yeh; Kuo-Liang Cheng; Yung-Fa Chou; Cheng-Wen Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

CAD reference flow for 3D via-last integrated circuits. - Chang-Tzu Lin; Ding-Ming Kwai; Yung-Fa Chou; Ting-Sheng Chen; Wen Ching Wu (ASP-DAC, 2010)

A Test Integration Methodology for 3D Integrated Circuits. - Che-Wei Chou; Jin-Fu Li 001; Ji-Jan Chen; Ding-Ming Kwai; Yung-Fa Chou; Cheng-Wen Wu (Asian Test Symposium, 2010)

Performance Characterization of TSV in 3D IC via Sensitivity Analysis. - Jhih-Wei You; Shi-Yu Huang; Ding-Ming Kwai; Yung-Fa Chou; Cheng-Wen Wu (Asian Test Symposium, 2010)

A self-testing and calibration method for embedded successive approximation register ADC. - Xuan-Lun Huang; Ping-Ying Kang; Hsiu-Ming Chang 001; Jiun-Lang Huang; Yung-Fa Chou; Yung-Pin Lee; Ding-Ming Kwai; Cheng-Wen Wu (ASP-DAC, 2011)

A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager. - Xuan-Lun Huang; Ping-Ying Kang; Jiun-Lang Huang; Yung-Fa Chou; Yung-Pin Lee; Ding-Ming Kwai (ETS, 2011)

A built-in self-test scheme for the post-bond test of TSVs in 3D ICs. - Yu-Jen Huang; Jin-Fu Li 001; Ji-Jan Chen; Ding-Ming Kwai; Yung-Fa Chou; Cheng-Wen Wu (VTS, 2011)

Yield Enhancement by Bad-Die Recycling and Stacking With Though-Silicon Vias. - Yung-Fa Chou; Ding-Ming Kwai; Cheng-Wen Wu (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Small delay testing for TSVs in 3-D ICs. - Shi-Yu Huang; Yu-Hsiang Lin; Kun-Han Tsai; Wu-Tung Cheng; Stephen K. Sunter; Yung-Fa Chou; Ding-Ming Kwai (DAC, 2012)

A built-in self-test scheme for 3D RAMs. - Yun-Chao You; Che-Wei Chou; Jin-Fu Li 001; Chih-Yen Lo; Ding-Ming Kwai; Yung-Fa Chou; Cheng-Wen Wu (ITC, 2012)

3D-IC BISR for stacked memories using cross-die spares. - Chun-Chuan Chi; Yung-Fa Chou; Ding-Ming Kwai; Yu-Ying Hsiao; Cheng-Wen Wu; Yu-Tsao Hsing; Li-Ming Denq; Tsung-Hsiang Lin (VLSI-DAT, 2012)

3-D centric technology and realization with TSV. - Chang-Tzu Lin; Chia-Hsin Lee; Tsu-Wei Tseng; Ding-Ming Kwai; Yung-Fa Chou (VLSI-DAT, 2012)

A SAR ADC missing-decision level detection and removal technique. - Jiun-Lang Huang; X.-L. Huang; Yung-Fa Chou; Ding-Ming Kwai (VTS, 2012)

An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration. - Xuan-Lun Huang; Jiun-Lang Huang; Hung-I Chen; Chang-Yu Chen; Tseng Kuo-Tsai; Ming-Feng Huang; Yung-Fa Chou; Ding-Ming Kwai (J. Electron. Test., 2012)

I-LUTSim: An iterative look-up table based thermal simulator for 3-D ICs. - Chi-Wen Pan; Yu-Min Lee; Pei-Yu Huang; Chi-Ping Yang; Chang-Tzu Lin; Chia-Hsin Lee; Yung-Fa Chou; Ding-Ming Kwai (ASP-DAC, 2013)

An FPGA-based test platform for analyzing data retention time distribution of DRAMs. - Chih-Sheng Hou; Jin-Fu Li 001; Chih-Yen Lo; Ding-Ming Kwai; Yung-Fa Chou; Cheng-Wen Wu (VLSI-DAT, 2013)

Worst-case IR-drop monitoring with 1GHz sampling rate. - Chen-Hsiang Hsu; Shi-Yu Huang; Ding-Ming Kwai; Yung-Fa Chou (VLSI-DAT, 2013)

Enabling inter-die co-optimization in 3-D IC with TSVs. - Chang-Tzu Lin; Tsu-Wei Tseng; Yung-Fa Chou; Chia-Hsin Lee; Ding-Ming Kwai (VLSI-DAT, 2013)

A hybrid ECC and redundancy technique for reducing refresh power of DRAMs. - Yun-Chao You; Chih-Sheng Hou; Li-Jung Chang; Jin-Fu Li 001; Chih-Yen Lo; Ding-Ming Kwai; Yung-Fa Chou; Cheng-Wen Wu (VTS, 2013)

Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis. - Yu-Hsiang Lin; Shi-Yu Huang; Kun-Han Tsai; Wu-Tung Cheng; Stephen K. Sunter; Yung-Fa Chou; Ding-Ming Kwai (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Reactivation of Spares for Off-Chip Memory Repair After Die Stacking in a 3-D IC With TSVs. - Yung-Fa Chou; Ding-Ming Kwai; Ming-Der Shieh; Cheng-Wen Wu (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Die-to-Die Clock Synchronization for 3-D IC Using Dual Locking Mechanism. - Ji-Wei Ker; Shi-Yu Huang; Chao-Wen Tzeng; Ding-Ming Kwai; Yung-Fa Chou (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis. - Jhih-Wei You; Shi-Yu Huang; Yu-Hsiang Lin; Meng-Hsiu Tsai; Ding-Ming Kwai; Yung-Fa Chou; Cheng-Wen Wu (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs. - Kuan-Te Wu; Jin-Fu Li 001; Yun-Chao Yu; Chih-Sheng Hou; Chi-Chun Yang; Ding-Ming Kwai; Yung-Fa Chou; Chih-Yen Lo (ATS, 2014)

BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs. - Yun-Chao You; Chi-Chun Yang; Jin-Fu Li 001; Chih-Yen Lo; Chao-Hsun Chen; Jenn-Shiang Lai; Ding-Ming Kwai; Yung-Fa Chou; Cheng-Wen Wu (ATS, 2014)

A power delivery network (PDN) engineering change order (ECO) approach for repairing IR-drop failures after the routing stage. - Tsu-Wei Tseng; Chang-Tzu Lin; Chia-Hsin Lee; Yung-Fa Chou; Ding-Ming Kwai (VLSI-DAT, 2014)

Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults. - Yen-Lin Peng; Ding-Ming Kwai; Yung-Fa Chou; Cheng-Wen Wu (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Temperature-aware online testing of power-delivery TSVs. - Hua-Cheng Fu; Shi-Yu Huang; Ding-Ming Kwai; Yung-Fa Chou (3DIC, 2015)

A hybrid built-in self-test scheme for DRAMs. - Chi-Chun Yang; Jin-Fu Li 001; Yun-Chao Yu; Kuan-Te Wu; Chih-Yen Lo; Chao-Hsun Chen; Jenn-Shiang Lai; Ding-Ming Kwai; Yung-Fa Chou (VLSI-DAT, 2015)

A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs. - Pei-Wen Luo; Chi-Kang Chen; Yu-Hui Sung; Wei Wu 024; Hsiu-Chuan Shih; Chia-Hsin Lee; Kuo-Hua Lee; Ming-Wei Li; Mei-Chiang Lung; Chun-Nan Lu; Yung-Fa Chou; Po-Lin Shih; et al. (VLSIC, 2015)

Hierarchical Test Integration Methodology for 3-D ICs. - Che-Wei Chou; Jin-Fu Li 001; Yun-Chao Yu; Chih-Yen Lo; Ding-Ming Kwai; Yung-Fa Chou (IEEE Des. Test, 2015)

A Test Method for Finding Boundary Currents of 1T1R Memristor Memories. - Tzu-Ying Lin; Yong-Xiao Chen; Jin-Fu Li 001; Chih-Yen Lo; Ding-Ming Kwai; Yung-Fa Chou (ATS, 2016)

A built-in self-repair scheme for DRAMs with spare rows, columns, and bits. - Chih-Sheng Hou; Yong-Xiao Chen; Jin-Fu Li 001; Chih-Yen Lo; Ding-Ming Kwai; Yung-Fa Chou (ITC, 2016)

Heterogeneous chip power delivery modeling and co-synthesis for practical 3DIC realization. - Wei-Hsun Liao; Chang-Tzu Lin; Sheng-Hsin Fang; Chien-Chia Huang; Hung-Ming Chen; Ding-Ming Kwai; Yung-Fa Chou (ASP-DAC, 2017)

DLL-Assisted Clock Synchronization Method for Multi-Die ICs. - Chia-Yuan Cheng; Shi-Yu Huang; Ding-Ming Kwai; Yung-Fa Chou (ICCD, 2017)

23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache. - Tah-Kang Joseph Ting; Gyh-Bin Wang; Ming-Hung Wang; Chun-Peng Wu; Chun-Kai Wang; Chun-Wei Lo; Li-Chin Tien; Der-Min Yuan; Yung-Ching Hsieh; Jenn-Shiang Lai; Wen-Pin Hsu; Chien-Chih Huang; et al. (ISSCC, 2017)

On Tolerating Faults of TSV/Microbumps for Power Delivery Networks in 3D IC. - Sheng-Hsin Fang; Chang-Tzu Lin; Wei-Hsun Liao; Chien-Chia Huang; Li-Chin Chen; Hung-Ming Chen; I-Hsuan Lee; Ding-Ming Kwai; Yung-Fa Chou (ISVLSI, 2017)

Resilient Cell-Based Architecture for Time-to-Digital Converter. - Chia-Hua Wu; Shi-Yu Huang; Mason Chern; Yung-Fa Chou; Ding-Ming Kwai (ISVLSI, 2017)

Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs. - Tsung-Fu Hsieh; Jin-Fu Li 001; Kuan-Te Wu; Jenn-Shiang Lai; Chih-Yen Lo; Ding-Ming Kwai; Yung-Fa Chou (ITC-Asia, 2017)

A channel-sharable built-in self-test scheme for multi-channel DRAMs. - Kuan-Te Wu; Jin-Fu Li 001; Chih-Yen Lo; Jenn-Shiang Lai; Ding-Ming Kwai; Yung-Fa Chou (ASP-DAC, 2018)

RRAM-Based Neuromorphic Hardware Reliability Improvement by Self-Healing and Error Correction. - Jia-Yun Hu; Kuan-Wei Hou; Chih-Yen Lo; Yung-Fa Chou; Cheng-Wen Wu (ITC-Asia, 2018)

Refresh Power Reduction of DRAMs in DNN Systems Using Hybrid Voting and ECC Method. - Tsung-Fu Hsieh; Jin-Fu Li 001; Jenn-Shiang Lai; Chih-Yen Lo; Ding-Ming Kwai; Yung-Fa Chou (ITC-Asia, 2020)

Time-to-Digital Converter Compiler for On-Chip Instrumentation. - Chia-Hua Wu; Shi-Yu Huang; Yung-Fa Chou; Ding-Ming Kwai (IEEE Des. Test, 2020)