A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC. - Yung-Hui Chung; Jieh-Tsorng Wu (IEEE J. Solid State Circuits, 2010)

A 24μW 12b 1MS/s 68.3dB SNDR SAR ADC with two-step decision DAC switching. - Yung-Hui Chung; Meng-Hsuan Wu; Hung-Sung Li (CICC, 2013)

The swapping binary-window DAC switching technique for SAR ADCs. - Yung-Hui Chung (ISCAS, 2013)

Perturbation-based digital background calibration technique for pipelined ADCs. - Yung-Hui Chung (ISCAS, 2014)

A 5-b 1-GS/s 2.7-mW binary-search ADC in 90nm digital CMOS. - Yung-Hui Chung; Cheng-Hsun Tsai; Hsuan-Chin Yeh (SoCC, 2015)

A 12-bit 8.47-fJ/Conversion-Step Capacitor-Swapping SAR ADC in 110-nm CMOS. - Yung-Hui Chung; Meng-Hsuan Wu; Hung-Sung Li (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A 16-mW 8-Bit 1-GS/s Digital-Subranging ADC in 55-nm CMOS. - Yung-Hui Chung; Jieh-Tsorng Wu (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A 5-b 1-GS/s binary-search ADC in 90nm CMOS. - Yung-Hui Chung; Cheng-Hsun Tsai; Hsuan-Chih Yeh (APCCAS, 2016)

A PVT-tracking metastability detector for asynchronous ADCs. - Yung-Hui Chung; Chia-Wei Yen (ISCAS, 2016)

A 24- μW 12-bit 1-MS/s SAR ADC With Two-Step Decision DAC Switching in 110-nm CMOS. - Yung-Hui Chung; Chia-Wei Yen; Meng-Hsuan Wu (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A 12-bit 160-MS/s ping-pong subranged-SAR ADC in 65nm CMOS. - Yung-Hui Chung; Ya-Mien Hsu; Chia-Wei Yen; Wei-Shu Rih (ISOCC, 2017)

A 6-bit 1.6-GS/s domino-SAR ADC in 55nm CMOS. - Yung-Hui Chung; Wei-Shu Rih (ISOCC, 2017)

A 10-bit 100-MS/s SAR ADC with capacitor swapping technique in 90-nm CMOS. - Yung-Hui Chung; Song-You Shih (VLSI-DAT, 2017)

A 5-bit 1-GS/s binary-search ADC in 90-nm CMOS. - Yung-Hui Chung; Cheng-Hsun Tsai; Hsuan-Chih Yeh (Microelectron. J., 2017)

An 11-bit 100-MS/s Subranged-SAR ADC in 65-nm CMOS. - Yung-Hui Chung; Chia-Wei Yen (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A 12-bit 20-MS/s SAR ADC With Fast-Binary-Window DAC Switching in 180nm CMOS. - Yung-Hui Chung; Yi-Shen Lin; Qi-Feng Zeng (APCCAS, 2018)

A 38-mW 7-bit 5-GS/s Time-Interleaved SAR ADC with Background Skew Calibration. - Yung-Hui Chung; Chia-Yi Hu; Che-Wei Chang (A-SSCC, 2018)

A 12-bit 10-MS/s SAR ADC with a binary-window DAC switching scheme in 180-nm CMOS. - Yung-Hui Chung; Chia-Wei Yen; Pei-Kang Tsai (Int. J. Circuit Theory Appl., 2018)

A 6-bit 1.3-GS/s Ping-Pong Domino-SAR ADC in 55-nm CMOS. - Yung-Hui Chung; Wei-Shu Rih; Che-Wei Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 12-bit 40-MS/s SAR ADC With a Fast-Binary-Window DAC Switching Scheme. - Yung-Hui Chung; Chia-Wei Yen; Pei-Kang Tsai; Bo-Wei Chen (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A 12-bit Domino ADC with a Background Offset Calibration Scheme. - Yung-Hui Chung (APCCAS, 2019)

A 102dB-SFDR 16-bit Calibration-Free SAR ADC in 180-nm CMOS. - Yung-Hui Chung; Chia-Hui Tien; Qi-Feng Zeng (APCCAS, 2019)

A 12-Bit Synchronous-SAR ADC for IoT Applications. - Yung-Hui Chung; Min-Sheng Chiang (ISCAS, 2019)

A 12-Bit 100-MS/s Subrange SAR ADC With a Foreground Offset Tracking Calibration Scheme. - Yung-Hui Chung; Ya-Mien Hsu (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 12-bit 100-kS/s SAR ADC for IoT Applications. - Yung-Hui Chung; Qi-Feng Zeng (VLSI-DAT, 2020)

A 12-bit SAR ADC With a DAC-Configurable Window Switching Scheme. - Yung-Hui Chung; Qi-Feng Zeng; Yi-Shen Lin (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A 3-mW 12b 160-MS/s 2-Way Time-Interleaved Subrange SAR ADC in 65-nm CMOS. - Yung-Hui Chung; Wei-Shu Rih (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A Resistor-Less CMOS Bandgap Reference with High-Order Temperature Compensation. - Yung-Hui Chung; Jia-Fong Shih; Yu-Hsiang Wang (APCCAS, 2021)

An 8-Bit 1.25-GS/s 2.5-GHz ERBW Folding-Subrange ADC with Power-Efficient Metastability Error Reduction Technique. - Bo-Wei Chen; Yung-Hui Chung; Chia-Ming Tsai (VLSI-DAT, 2021)

A 16-Bit Calibration-Free SAR ADC With Binary-Window and Capacitor-Swapping DAC Switching Schemes. - Yung-Hui Chung; Chia-Hui Tien; Qi-Feng Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 90-dB DR Discrete-Time Delta-Sigma Modulator for Audio Applications. - Hou-Hsuan Lin; Jia-Fong Shih; Yung-Hui Chung (ISOCC, 2023)

A 91.7-dB SNDR Discrete-Time Zoom ADC with a 20-kHz BW in 180-nm CMOS. - Zi-Chi Lin; Chun-Yang Chiu; Yung-Hui Chung (APCCAS, 2024)

A 12b Dual-Mode SAR ADC for Bio-Medical Applications. - Yung-Hui Chung; Jyun-Hau Kuo (BioCAS, 2024)

A 10b 400MS/s 2x-Time-Interleaved 2-Then-1b/Cycle SAR ADC in 90nm CMOS. - Wei-Chung Lin; Yung-Chi Chang; Yung-Hui Chung (ISCAS, 2024)

A 105-dB SFDR 16-bit SAR ADC with a Window Capacitor Calibration Scheme. - Qi-Fen Zeng; Chia-Hui Tien; Yung-Hui Chung (ISCAS, 2024)

A 12-bit SAR ADC Utilizing Background Capacitor Calibration with LLM-LMS Algorithm. - Chung-Wei Lin; Yung-Hui Chung (ISCAS, 2025)