A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors. - Zhixiao Zhang; Jia-Jing Chen; Xin Si; Yung-Ning Tu; Jian-Wei Su; Wei-Hsing Huang; Jing-Hong Wang; Wei-Chen Wei; Yen-Cheng Chiu; Je-Min Hong; Shyh-Shyuan Sheu; Sih-Han Li; et al. (A-SSCC, 2019)

Monolithic-3D Integration Augmented Design Techniques for Computing in SRAMs. - Srivatsa Rangachar Srinivasa; Wei-Hao Chen; Yung-Ning Tu; Meng-Fan Chang; Jack Sampson; Vijaykrishnan Narayanan (ISCAS, 2019)

A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning. - Xin Si; Jia-Jing Chen; Yung-Ning Tu; Wei-Hsing Huang; Jing-Hong Wang; Yen-Cheng Chiu; Wei-Chen Wei; Ssu-Yen Wu; Xiaoyu Sun 001; Rui Liu 005; Shimeng Yu; Ren-Shuo Liu; et al. (ISSCC, 2019)

A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1 × Higher TOPS/mm2and 6T HBST-TRAM-Based 2D Data-Reuse Architecture. - Jinshan Yue; Ruoyang Liu; Wenyu Sun; Zhe Yuan; Zhibo Wang 004; Yung-Ning Tu; Yi-Ju Chen; Ao Ren; Yanzhi Wang; Meng-Fan Chang; Xueqing Li 002; Huazhong Yang; et al. (ISSCC, 2019)

15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips. - Xin Si; Yung-Ning Tu; Wei-Hsing Huang; Jian-Wei Su; Pei-Jung Lu; Jing-Hong Wang; Ta-Wei Liu; Ssu-Yen Wu; Ruhui Liu; Yen-Chi Chou; Zhixiao Zhang; Syuan-Hao Sie; et al. (ISSCC, 2020)

15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips. - Jian-Wei Su; Xin Si; Yen-Chi Chou; Ting-Wei Chang; Wei-Hsing Huang; Yung-Ning Tu; Ruhui Liu; Pei-Jung Lu; Ta-Wei Liu; Jing-Hong Wang; Zhixiao Zhang; Hongwu Jiang; et al. (ISSCC, 2020)

A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors. - Yen-Cheng Chiu; Zhixiao Zhang; Jia-Jing Chen; Xin Si; Ruhui Liu; Yung-Ning Tu; Jian-Wei Su; Wei-Hsing Huang; Jing-Hong Wang; Wei-Chen Wei; Je-Min Hung; Shyh-Shyuan Sheu; et al. (IEEE J. Solid State Circuits, 2020)

A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors. - Xin Si; Rui Liu 005; Shimeng Yu; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Qiang Li 021; Meng-Fan Chang; Jia-Jing Chen; Yung-Ning Tu; Wei-Hsing Huang; Jing-Hong Wang; et al. (IEEE J. Solid State Circuits, 2020)

A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips. - Xin Si; Yung-Ning Tu; Wei-Hsing Huang; Jian-Wei Su; Pei-Jung Lu; Jing-Hong Wang; Ta-Wei Liu; Ssu-Yen Wu; Ruhui Liu; Yen-Chi Chou; Yen-Lin Chung; William Shih; et al. (IEEE J. Solid State Circuits, 2021)

STICKER-T: An Energy-Efficient Neural Network Processor Using Block-Circulant Algorithm and Unified Frequency-Domain Acceleration. - Jinshan Yue; Yongpan Liu; Ruoyang Liu; Wenyu Sun; Zhe Yuan; Yung-Ning Tu; Yi-Ju Chen; Ao Ren; Yanzhi Wang; Meng-Fan Chang; Xueqing Li 002; Huazhong Yang (IEEE J. Solid State Circuits, 2021)

Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips. - Jian-Wei Su; Xin Si; Yen-Chi Chou; Ting-Wei Chang; Wei-Hsing Huang; Yung-Ning Tu; Ruhui Liu; Pei-Jung Lu; Ta-Wei Liu; Jing-Hong Wang; Yen-Lin Chung; Jin-Sheng Ren; et al. (IEEE J. Solid State Circuits, 2022)