A phase locked loop with a mixed mode loop filter for clock/data recovery in optical disc drives. - Ping-Ying Wang; Hsiang Ji Hsieh; Yung-Yu Lin; Meng-Ta Yang; Hsueh-Wu Kao (ISCAS (5), 2005)

A 1.2V 2MHz BW 0.084mm2 CT ΔΣ ADC with -97.7dBc THD and 80dB DR using low-latency DEM. - Sheng-Jui Huang; Yung-Yu Lin (ISSCC, 2009)

Dual-mode Continuous-Time Quadrature Bandpass ΔΣ modulator with Pseudo-random Quadrature mismatch shaping algorithm for Low-IF receiver application. - Chen-Yen Ho; Yung-Yu Lin; Tsung-Hsien Lin (ISCAS, 2010)

A Quadrature Bandpass Continuous-Time Delta-Sigma Modulator for a Tri-Mode GSM-EDGE/UMTS/DVB-T Receiver. - Chen-Yen Ho; Wei-Shan Chan; Yung-Yu Lin; Tsung-Hsien Lin (IEEE J. Solid State Circuits, 2011)

LMS-based digital background linearization technique for VCO-based delta-sigma ADC. - Fu-Chien Huang; Shou-Chen Hsu; Yi-Lin Tsai; Yung-Yu Lin; Tsung-Hsien Lin (MWSCAS, 2014)

A TDC-Based Two-Step Quantizer With Swapper Technique for a Multibit Continuous-Time Delta-Sigma Modulator. - Chen-Chien Lin; Chan-Hsiang Weng; Tzu-An Wei; Yung-Yu Lin; Tsung-Hsien Lin (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

The prediction system for data analysis of stock market by using Genetic Algorithm. - Ching-Te Wang; Yung-Yu Lin (FSKD, 2015)

A 1-V 5-MHz Bandwidth 68.3-dB SNDR Continuous-Time Delta-Sigma Modulator With a Feedback-Assisted Quantizer. - Chan-Hsiang Weng; Yung-Yu Lin; Tsung-Hsien Lin (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)