SRAM-Based Digital CIM Macro for Linear Interpolation and MAC. - Zhiting Lin; Yunlong Liu 006; Yaling Wang; Yue Zhao 029; Chunyu Peng; Xiulong Wu (ISCAS, 2024)

Configurable in-memory computing architecture based on dual-port SRAM. - Yue Zhao 029; Yunlong Liu 006; Jian Zheng; Zhongzhen Tong; Xin Wang; Runru Yu; Xiulong Wu; Yongliang Zhou; Chunyu Peng; Wenjuan Lu; Qiang Zhao 007; Zhiting Lin (Microelectron. J., 2024)

A High Throughput In-MRAM-Computing Scheme Using Hybrid p-SOT-MTJ/GAA-CNTFET. - Zhongzhen Tong; Yilin Xu; Yunlong Liu 006; Xinrui Duan; Hao Tang; Suteng Zhao; Chenghang Li; Zhiting Lin; Xiulong Wu; Zhaohao Wang; Xiaoyang Lin (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design. - Licai Hao; Yaling Wang; Yunlong Liu 006; Shiyu Zhao 004; Xinyi Zhang; Yang Li; Wenjuan Lu; Chunyu Peng; Qiang Zhao 007; Yongliang Zhou; Chenghu Dai; Zhiting Lin; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A 0.000159 mm2 2.9 μm-pitch 4.3fJ/Conv 6-bit SAR ADC for high throughput parallel readout of analog SRAM computing-in-memory. - Lin Wu; Lichen Feng; Yunlong Liu 006; Libo Qian; Yinshui Xia; Zhangming Zhu (Microelectron. J., 2025)

Improving MAC Accuracy of Pre-Aligned Floating-Point CIM Macros for Compound AI with Statistical Group Features. - Yunlong Liu 006; Lichen Feng; Dong Li 046; Zhangming Zhu (ISCAS, 2026)

30.4 A 28nm 106.85TOPS/W and 77.68TFLOPS/W CIM Macro with Stage-Wise-Enabled Lossless Compressors Based on Sign-Bit-Embedded Transition-Counting-Lines for Edge-AI Devices. - Lichen Feng; Yunlong Liu 006; Lin Wu; Dong Li 046; Zhangming Zhu (ISSCC, 2026)

Analysis and Design of Memory Testing Algorithm for Computing-in-Memory Using MBIST. - Zhiting Lin; Siyan Li; Qiuming Zhang; Qiushi Feng; Changxin Yue; Jiaqi Chen; Yuanyang Wang; Yunlong Liu 006; Yu Liu 113; Licai Hao; Chunyu Peng; Qiang Zhao 007; et al. (ACM J. Emerg. Technol. Comput. Syst., 2026)