A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture. - Kibong Koo; Sunghwa Ok; Yonggu Kang; Seungbong Kim; Choungki Song; Hyeyoung Lee; Hyungsoo Kim; Yongmi Kim; Jeonghun Lee; Seunghan Oak; Yosep Lee; Jungyu Lee 002; et al. (ISSCC, 2012)

A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface. - Hyun-Woo Lee; Soo-Bin Lim; Junyoung Song; Jabeom Koo; Dae-Han Kwon; Jong-Ho Kang; Yunsaing Kim; Young-Jung Choi; Kunwoo Park; Byong-Tae Chung; Chulwoo Kim (ISSCC, 2012)

A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces. - Hyun-Woo Lee; Hoon Choi; Beom-Ju Shin; Kyung-Hoon Kim; Kyung Whan Kim; Jaeil Kim; Kwang Hyun Kim; Jongho Jung; Jae-Hwan Kim; Eun Young Park; Jong-Sam Kim; Jong-Hwan Kim; et al. (IEEE J. Solid State Circuits, 2012)

A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z0 at both TX and RX. - Soo-Min Lee; Jong-Hoon Kim; Jong-Sam Kim; Yunsaing Kim; Hyunbae Lee; Jae-Yoon Sim; Hong-June Park (ISSCC, 2013)

An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface. - Junyoung Song; Hyun-Woo Lee; Soo-Bin Lim; Sewook Hwang; Yunsaing Kim; Young-Jung Choi; Byong-Tae Chung; Chulwoo Kim (ISSCC, 2013)

A 16.8Gbps/channel single-ended transceiver in 65nm CMOS for SiP based DRAM interface on Si-carrier channel. - Hyunbae Lee; Taeksang Song; Sangyeon Byeon; Kwanghun Lee; Inhwa Jung; Seongjin Kang; Ohkyu Kwon; Koeun Cheon; Donghwan Seol; Jong-Ho Kang; Gunwoo Park; Yunsaing Kim (A-SSCC, 2014)

25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector. - Hyun-Woo Lee; Junyoung Song; Sangah Hyun; Seunggeun Baek; Yuri Lim; Jungwan Lee; Minsu Park; Haerang Choi; Changkyu Choi; Jin-Youp Cha; Jaeil Kim; Hoon Choi; et al. (ISSCC, 2014)

An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface. - Soo-Min Lee; Il-Min Yi; Hae-Kang Jung; Hyunbae Lee; Yong-Ju Kim; Yunsaing Kim; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE J. Solid State Circuits, 2014)

Crosstalk-included eye-diagram estimation for high-speed silicon, organic, and glass interposer channels on 2.5D/3D IC. - Sumin Choi; Heegon Kim; Daniel H. Jung; Jonghoon J. Kim; Jaemin Lim; Hyunsuk Lee; Kyungjun Cho; Joungho Kim; Hyungsoo Kim; Yong-Ju Kim; Yunsaing Kim (3DIC, 2015)

A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications. - Hae-Kang Jung; Jaemo Yang; Jeonghun Lee; Hyeongjun Ko; Hyuk Lee; Taeksang Song; Jongjoo Shim; Sangkwon Lee; Keunsoo Song; Dongkyun Kim; Hyungsoo Kim; Yunsaing Kim (VLSIC, 2015)

A 16.8 Gbps/Channel Single-Ended Transceiver in 65 nm CMOS for SiP-Based DRAM Interface on Si-Carrier Channel. - Hyunbae Lee; Taeksang Song; Sangyeon Byeon; Kwanghun Lee; Inhwa Jung; Seongjin Kang; Ohkyu Kwon; Koeun Cheon; Donghwan Seol; Jong-Ho Kang; Gunwoo Park; Yunsaing Kim (IEEE J. Solid State Circuits, 2015)