A Custom IC Layout Generation Engine Based on Dynamic Templates and Grids. - Taeho Shin; Dongjun Lee; Dongwhee Kim; Gaeryun Sung; Wookjin Shin; Yunseong Jo; Hyungjoo Park; Jaeduk Han (CoRR, 2022)

The effect of virtual reality media characteristics on flow and learning transfer in job training: The moderating effect of presence. - Youn Gu Kang; Hae-Deok Song; Hyejoo Yun; Yunseong Jo (J. Comput. Assist. Learn., 2022)

An 8b9b 77.44-Gb/s Noise-Immune Spatial-Delta Coded Transceiver for Short-Reach Memory Interfaces in 28-nm CMOS. - Hyuntae Kim; Hyeongmin Seo; Yunseong Jo; Changsik Yoo; Jaeduk Han (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

LAYGO2: A Custom Layout Generation Engine Based on Dynamic Templates and Grids for Advanced CMOS Technologies. - Taeho Shin; Dongjun Lee; Dongwhee Kim; Gaeryun Sung; Wookjin Shin; Yunseong Jo; Hyungjoo Park; Jaeduk Han (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Analysis of Test Environment Configuration for High-Speed Link Chip Measurement. - Yunseong Jo; Hyuntae Kim; Jaeduk Han (ISOCC, 2024)

A 32-Gb/s Single-Ended PAM-4 Transceiver With Asymmetric Termination and Equalization Techniques for Next-Generation Memory Interfaces. - Hyuntae Kim; Yunseong Jo; Sanghun Lee; Eunsang Lee; Young Choi; Jaewoo Park; Myoungbo Kwak; Jung-Hwan Choi; Youngdon Choi; Jaeduk Han (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 500-MS/s 8-bit SAR ADC Generated from an Automated Layout Generation Framework in 14-nm FinFET Technology. - Yunseong Jo; Taeseung Kang; Jeonghyu Yang; Jaeduk Han (ASP-DAC, 2025)

22.4 A 32-to-50Gb/s/pin Single-Ended PAM-4 Transmitter with a ZQ-Based FFE and PAM-4 LSB DBI-DC Encoding. - Yunseong Jo; Hyuntae Kim; Young Choi; Jaewoo Park; Myoungbo Kwak; Jaeduk Han (ISSCC, 2025)