Energy-Efficient Arbitrary Precision Multi-Bit Multiplication with Bi-Serial In/Near Memory Computing. - Yuqi Wang 004; Jian Chen; Yu Pu; Yajun Ha (ISCAS, 2020)

Analysis and Optimization Strategies Toward Reliable and High-Speed 6T Compute SRAM. - Jian Chen; Wenfeng Zhao; Yuqi Wang 004; Yajun Ha (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Analysis and Design of Reconfigurable Sense Amplifier for Compute SRAM With High-Speed Compute and Normal Read Access. - Jian Chen; Wenfeng Zhao; Yuqi Wang 004; Yajun Ha (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations. - Jian Chen; Wenfeng Zhao; Yuqi Wang 004; Yuhao Shu; Weixiong Jiang; Yajun Ha (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A 40nm 0.35V 25MHz Half-Select Disturb-Free Bitinterleaving 10T SRAM With Data-Aware Write-Path. - Yifei Li; Jian Chen; Yuqi Wang 004; Zihan Yin; Hongyu Chen; Yajun Ha (CICC, 2023)

A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-VDD Assist and Bitline Leakage Compensation. - Yuqi Wang 004; Shen Zhang; Yifei Li; Jian Chen; Wenfeng Zhao; Yajun Ha (IEEE Trans. Very Large Scale Integr. Syst., 2023)