ACF: Networks-on-Chip Deadlock Recovery with Accurate Detection and Elastic Credit. - Nan Wu 003; Yuran Qiao; Mei Wen; Chunyuan Zhang (APPT, 2013)

Automated Transformation of GPU-Specific OpenCL Kernels Targeting Performance Portability on Multi-Core/Many-Core CPUs. - Dafei Huang; Mei Wen; Changqing Xun; Dong Chen 015; Xing Cai; Yuran Qiao; Nan Wu 003; Chunyuan Zhang (Euro-Par, 2014)

Unified Virtual Memory Support for Deep CNN Accelerator on SoC FPGA. - Tao Xiao; Yuran Qiao; Junzhong Shen; Qianming Yang; Mei Wen (ICA3PP (1), 2015)

Optimizing OpenCL Implementation of Deep Convolutional Neural Network on FPGA. - Yuran Qiao; Junzhong Shen; Dafei Huang; Qianming Yang; Mei Wen; Chunyuan Zhang (NPC, 2017)

FPGA-accelerated deep convolutional neural networks for high throughput and energy efficiency. - Yuran Qiao; Junzhong Shen; Tao Xiao; Qianming Yang; Mei Wen; Chunyuan Zhang (Concurr. Comput. Pract. Exp., 2017)

Towards a Uniform Template-based Architecture for Accelerating 2D and 3D CNNs on FPGA. - Junzhong Shen; You Huang; Zelong Wang; Yuran Qiao; Mei Wen; Chunyuan Zhang (FPGA, 2018)

Towards a Multi-array Architecture for Accelerating Large-scale Matrix Multiplication on FPGAs. - Junzhong Shen; Yuran Qiao; You Huang; Mei Wen; Chunyuan Zhang (ISCAS, 2018)

MALMM: A multi-array architecture for large-scale matrix multiplication on FPGA. - You Huang; Junzhong Shen; Yuran Qiao; Mei Wen; Chunyuan Zhang (IEICE Electron. Express, 2018)

Heterogeneous Systolic Array Architecture for Compact CNNs Hardware Accelerators. - Rui Xu; Sheng Ma; Yaohua Wang; Yang Guo 003; Dongsheng Li 001; Yuran Qiao (IEEE Trans. Parallel Distributed Syst., 2022)