Linear transmitter design using high efficiency Class E power amplifier. - Tirdad Sowlati; Yuriy M. Greshishchev; C. André T. Salama; Gord Rabjohn; John Sitch (PIMRC, 1995)

Phase-correcting feedback system for class E power amplifier. - Tirdad Sowlati; Yuriy M. Greshishchev; C. André T. Salama (IEEE J. Solid State Circuits, 1997)

A 60-dB gain, 55-dB dynamic range, 10-Gb/s broad-band SiGe HBT limiting amplifier. - Yuriy M. Greshishchev; Peter Schvan (IEEE J. Solid State Circuits, 1999)

SiGe clock and data recovery IC with linear-type PLL for 10-Gb/s SONET application. - Yuriy M. Greshishchev; Peter Schvan (IEEE J. Solid State Circuits, 2000)

A fully integrated SiGe receiver IC for 10-Gb/s data rate. - Yuriy M. Greshishchev; Peter Schvan; Jonathan L. Showell; Mu-Liang Xu; Jugnu J. Ojha; Jonathan E. Rogers (IEEE J. Solid State Circuits, 2000)

Introduction to the Special Issue on the 2005 IEEE International Solid-State Circuits Conference. - Axel Thomsen; Jacques Christophe Rudell; Yuriy M. Greshishchev; J. E. D. Hurwitz (IEEE J. Solid State Circuits, 2005)

Optical Communications. - Sung Min Park 001; Yuriy M. Greshishchev (ISSCC, 2007)

Trends and Challenges in Optical Communications Front-End. - Yuriy M. Greshishchev; Takuji Yamamoto; Naresh R. Shanbhag (ISSCC, 2008)

A 24GS/s 6b ADC in 90nm CMOS. - Peter Schvan; Jérôme Bach; Chris Falt; Philip Flemke; Robert Gibbins; Yuriy M. Greshishchev; Naim Ben-Hamida; Daniel Pollex; John Sitch; Shing-Chi Wang; John Wolczanski (ISSCC, 2008)

Clock recovery for a 40 Gb/s QPSK optical receiver. - Naim Ben-Hamida; John Sitch; Philip Flemke; Daniel Pollex; Peter Schvan; Yuriy M. Greshishchev; Shing-Chi Wang; Chris Falt (ICECS, 2009)

A 40GS/s 6b ADC in 65nm CMOS. - Yuriy M. Greshishchev; Jorge Aguirre; Marinette Besson; Robert Gibbins; Chris Falt; Philip Flemke; Naim Ben-Hamida; Daniel Pollex; Peter Schvan; Shing-Chi Wang (ISSCC, 2010)

Transceiver circuits for optical communications. - Yuriy M. Greshishchev; Franz Dielacher; Michael Flynn; Donhee Ham; Naresh R. Shanbhag; Takuji Yamamoto (ISSCC, 2010)

A 56GS/S 6b DAC in 65nm CMOS with 256×6b memory. - Yuriy M. Greshishchev; Daniel Pollex; Shing-Chi Wang; Marinette Besson; Philip Flemeke; Stefan Szilagyi; Jorge Aguirre; Chris Falt; Naim Ben-Hamida; Robert Gibbins; Peter Schvan (ISSCC, 2011)

Coherent Transceiver for High Speed Optical Communications: Opportunities and Challenges. - Sebastien Blais; Yuriy M. Greshishchev; Peter Schvan; Ian Betty; Douglas McGhan (BCICTS, 2019)

A 60 GS/s 8-b DAC with > 29.5dB SINAD up to Nyquist frequency in 7nm FinFET CMOS. - Yuriy M. Greshishchev; Tingjun Wen; Naim Ben-Hamida; Jorge Aguirre; Sadok Aouini; Marinette Besson; Robert Gibbins; Young Gouk Cho; Jerry Lam; Douglas McPherson; Mahdi Parvizi (BCICTS, 2019)

Guest Editorial IEEE 2022 BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium. - Yuriy M. Greshishchev (IEEE J. Solid State Circuits, 2023)