Demystifying and Mitigating Code-Dependent Switching Distortions in Current-Steering DACs. - Longqiang Lai; Xueqing Li 002; Yushen Fu; Yongpan Liu; Huazhong Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 16-Bit 4.0-GS/s Calibration-Free 65nm DAC with >70dBc SFDR and <-80dBc IM3 up to 1GHz Using Constant-Activity Element Switching. - Chengyu Huang 001; Yushen Fu; Zekun Yang; Yang Liu; Nan Sun 001; Xueqing Li 002; Huazhong Yang (ESSCIRC, 2021)

Dynamic Switching Sequence to Compensate the Integral Nonlinearity in Current-Steering DACs. - Yang Liu; Yushen Fu; Chengyu Huang 001; Huazhong Yang; Xueqing Li 002 (ISCAS, 2021)

FAST: A Fully-Concurrent Access Technique to All SRAM Rows for Enhanced Speed and Energy Efficiency in Data-Intensive Applications. - Yiming Chen; Yushen Fu; Mingyen Lee; Sumitha George; Yongpan Liu; Vijaykrishnan Narayanan; Huazhong Yang; Xueqing Li 002 (CoRR, 2022)

A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration. - Yushen Fu; Chengyu Huang 001; Limeng Sun; Weiguang Meng; Xueqing Li 002; Huazhong Yang (IEEE Trans. Very Large Scale Integr. Syst., 2023)

FAST: A Fully-Concurrent Access SRAM Topology for High Row-Wise Parallelism Applications Based on Dynamic Shift Operations. - Yiming Chen; Yushen Fu; Mingyen Lee; Sumitha George; Yongpan Liu; Vijaykrishnan Narayanan; Huazhong Yang; Xueqing Li 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 16-Bit 4.0-GS/s Calibration-Free 65 nm DAC Achieving >70 dBc SFDR and < -80 dBc IM3 Up to 1 GHz With Enhanced Constant-Switching-Activity Data-Weighted-Averaging. - Yushen Fu; Chengyu Huang 001; Longqiang Lai; Nan Sun 001; Xueqing Li 002; Huazhong Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Competition in the online platform: impacts of blockchain technology adoption. - Yongwu Zhou; Yushen Fu; Kunyu Wang; Jie Min; Xiong Zhang (Int. Trans. Oper. Res., 2024)