A Study of the Lock Range of Injection-Locked CMOS Active-Inductor Oscillators Using a Linear Control System Approach. - Yushi Zhou; Fei Yuan 005 (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A frequency-domain study of lock range of harmonic oscillators with multiple injections. - Fei Yuan 005; Yushi Zhou (NEWCAS, 2012)

A Phasor-Domain Study of Lock Range of Harmonic Oscillators With Multiple Injections. - Fei Yuan 005; Yushi Zhou (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Low-power programmable charge-domain sampler with embedded N-path bandpass filter for software-defined radio. - Yushi Zhou; Norm M. Filiol; Shaul Peker; Fei Yuan 005 (ISCAS, 2013)

Frequency-Domain Study of Lock Range of Non-Harmonic Oscillators With Multiple Multi-Tone Injections. - Fei Yuan 005; Yushi Zhou (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Study of injection-locked non-harmonic oscillators using Volterra series. - Yushi Zhou; Fei Yuan 005 (IET Circuits Devices Syst., 2015)

A Quadrature Charge-Domain Sampling Mixer With Embedded FIR, IIR, and N-Path Filters. - Yushi Zhou; Norman M. Filiol; Fei Yuan 005 (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A spatial calibration method for satellite-derived precipitation estimates over China. - Fengrui Chen; Yushi Zhou; Wenting Wang (Geoinformatics, 2017)

Adaptive 4PAM decision feedback equalizer with reduced number of slicers. - Yushi Zhou; Fei Yuan 005 (MWSCAS, 2017)

A Comparative Study Of Injection Locked Frequency Divider Using Harmonic Mixer In Weak And Strong Inversion. - Yushi Zhou; Jared Mercier; Fei Yuan 005 (MWSCAS, 2018)

Suboptimal Class DE Operation for Ultrasound Transducer Arrays. - Carlos Christoffersen; Thinh Ngo; Ruiqi Song; Yushi Zhou; Samuel Pichardo; Laura Curiel (NEWCAS, 2018)

35 μW Linearized LNA for WSN Applications. - Jared Mercier; Yushi Zhou (MWSCAS, 2019)

A 500-MS/s 8.4-ps Double-Edge Successive Approximation TDC in 65 nm CMOS. - Rashed Siddiqui; Fei Yuan 005; Yushi Zhou (MWSCAS, 2019)

Quasi Class-DE Driving of HIFU Transducer Arrays. - Carlos Christoffersen; Thinh Ngo; Ruiqi Song; Yushi Zhou; Samuel Pichardo; Laura Curiel (ISCAS, 2020)

Area/Power-Efficient True-Single-Phase-Clock D-Flipflops with Improved Metastability. - Parth Parekh; Fei Yuan 005; Yushi Zhou (MWSCAS, 2020)

All-Digital Time Integrator Using Bi-Directional Gated Vernier Delay Line. - Parth Parekh; Fei Yuan 005; Yushi Zhou (MWSCAS, 2020)

All-Digital Successive Approximation TDC in Time-Mode Signal Processing. - Daniel Junehee Lee; Fei Yuan 005; Yushi Zhou (ISCAS, 2021)

Successive Approximation Register TDC in Time-Mode Signal Processing. - Daniel Junehee Lee; Fei Yuan 005; Yushi Zhou (MWSCAS, 2021)

Gated Vernier Delay Line Time Integrator for Time-Mode Signal Processing. - Parth Parekh; Fei Yuan 005; Yushi Zhou (MWSCAS, 2021)

An 8-bit digital-to-time converter with pre-skewing and time interpolation. - Daniel Junehee Lee; Fei Yuan 005; Gul N. Khan; Yushi Zhou (IET Circuits Devices Syst., 2021)

Low-power multi-band injection-locked wireless receiver in 0.13 μm CMOS. - Jared Mercier; Yushi Zhou (IET Circuits Devices Syst., 2021)

Design of High-Bandwidth, High-DC Gain Single-Stage Amplifier for High-Speed ADCs. - Ximing Fu; Yushi Zhou; Kamal El-Sankary (CCECE, 2022)

Bi-Directional Gated Ring Oscillator Time Integrator for Time-Based Mixed-Signal Processing. - Parth Parekh; Fei Yuan 005; Yushi Zhou (MWSCAS, 2022)

All-Digital Bi-Directional Gated Ring Oscillator Time Integrator for Mixed-Mode Signal Processing. - Parth Parekh; Fei Yuan 005; Yushi Zhou (NEWCAS, 2022)

Gated Vernier delay line time integrator with applications in ΔΣ time-to-digital converter. - Parth Parekh; Fei Yuan 005; Yushi Zhou (Microelectron. J., 2022)

Improved Metastability of True Single-Phase Clock D-Flipflops With Applications in Vernier Time-to-Digital Converters. - Parth Parekh; Fei Yuan 005; Yushi Zhou (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A High-Speed Capacitor Less LDO with Multi-Loop Fast Feedback and Bandwidth Enhancement Control. - Ximing Fu; Yushi Zhou; Pierre Leduc; Kamal El-Sankary (ISCAS, 2023)

A Cyclic Vernier Digital-to-Time Converter for Time-Mode Successive Approximation TDC. - Daniel Junehee Lee; Fei Yuan 005; Yushi Zhou (MWSCAS, 2023)

Time-Interpolated Vernier Digital-to-Time Converter with Applications in Time-Mode SAR TDC. - Daniel Junehee Lee; Fei Yuan 005; Yushi Zhou (NEWCAS, 2023)

Bi-Directional Gated Ring Oscillator Time Integrator. - Fei Yuan 005; Parth Parekh; Yushi Zhou (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Sub-Threshold Delay-Locked Loop with Piecewise Linearization and Time-Mode Proportional-Integral Locking. - Wenhao Wu; Fei Yuan 005; Yushi Zhou (APCCAS, 2024)

A 3.04-fs FoM Hybrid LDO Regulator with Fast Transient Algorithm and Wide Load Range. - Pierre Leduc; Ximing Fu; Yushi Zhou (MWSCAS, 2024)

A 0.6-V 108-nW 100-kHz Sub-Threshold Delay-Locked Loop with Digital Linearization for Low-Power SAR ADC. - Wenhao Wu; Fei Yuan 005; Yushi Zhou (MWSCAS, 2024)

A Dual Loop Current Mode Feedback Capacitor Less LDO for High Current Applications. - Pierre Leduc; Ximing Fu; Yushi Zhou; Kamal El-Sankary (NewCAS, 2024)

A 580-nA Quiescent Current Low-Dropout Regulator with Zero-Tracking for Wide Load Applications. - Zakary Williams; Lei Chen; Yushi Zhou; Zhanjun Bai (NewCAS, 2024)

Sub-Threshold All-Digital DLL for Clock Generation of SAR ADC. - Wenhao Wu; Fei Yuan 005; Yushi Zhou (IEEE Open J. Circuits Syst., 2025)

A 430-mA Capacitor Less Analog Assisted Hybrid LDO With Fast Transient Algorithm. - Pierre Leduc; Ximing Fu; Yushi Zhou (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)