An efficient method for circuit sensitivity calculation using piecewise linear waveform models. - Sung-Mo Kang; Yusuf Leblebici (ICCAD, 1988)

Simulation of MOS circuit performance degradation with emphasis on VLSI design-for-reliability. - Yusuf Leblebici; Sung-Mo Kang (ICCD, 1989)

An Integrated Hot-Carrier Degradation Simulator for VLSI Reliability Analysis. - Yusuf Leblebici; Sung-Mo Kang (ICCAD, 1990)

New Simulation Methods for MOS VLSI Timing and Reliability. - Yung-Ho Shih; Yusuf Leblebici; Sung-Mo Kang (ICCAD, 1991)

An accurate analytical delay model for BiCMOS driver circuits. - Carlos H. Díaz; Sung-Mo Kang; Yusuf Leblebici (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Modeling and simulation of hot-carrier induced device and circuit degradation for VLSI reliability - Yusuf Leblebici (1991)

Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation. - Yusuf Leblebici; Sung-Mo Kang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

ILLIADS: a fast timing and reliability simulator for digital MOS circuits. - Yung-Ho Shih; Yusuf Leblebici; Sung-Mo Kang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Modeling and simulation of hot-carrier-induced device degradation in MOS circuits. - Yusuf Leblebici; Sung-Mo Kang (IEEE J. Solid State Circuits, 1993)

Design considerations for CMOS digital circuits with improved hot-carrier reliability. - Yusuf Leblebici (IEEE J. Solid State Circuits, 1996)

A compact high-speed (31, 5) parallel counter circuit based on capacitive threshold-logic gates. - Yusuf Leblebici; Hakan Özdemir; Asim Kepkep; Ugur Çilingiroglu (IEEE J. Solid State Circuits, 1996)

A capacitive threshold-logic gate. - Hakan Özdemir; Asim Kepkep; Banu Pamir; Yusuf Leblebici; Ugur Çilingiroglu (IEEE J. Solid State Circuits, 1996)

A two-stage charge-based analog/digital neuron circuit with adjustable weights. - Alexandre Schmid; Yusuf Leblebici; Daniel Mlynek (IJCNN, 1999)

Realization of a programmable rank-order filter architecture using capacitive threshold logic gates. - Ilhan Hatirnaz; Frank K. Gürkaynak; Yusuf Leblebici (ISCAS (1), 1999)

A novel analog-digital flash converter architecture based on capacitive threshold gates. - Alexandre Schmid; D. Bowler; R. Baumgartner; Yusuf Leblebici (ISCAS (2), 1999)

A compact modular architecture for high-speed binary sorting. - Ilhan Hatirnaz; Frank K. Gürkaynak; Yusuf Leblebici (ICASSP, 2000)

Higher radix Kogge-Stone parallel prefix adder architectures. - Frank K. Gürkaynak; Yusuf Leblebici; Laurent Chaouat; Patrik J. McGuinness (ISCAS, 2000)

A compact modular architecture for the realization of high-speed binary sorting engines based on rank ordering. - Ilhan Hatirnaz; Frank K. Gürkaynak; Yusuf Leblebici (ISCAS, 2000)

A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic. - Ilhan Hatirnaz; Frank K. Gürkaynak; Yusuf Leblebici (VLSI Design, 2000)

VLSI Realization of a Two-Dimensional Hamming Distance Comparator ANN for Image Processing Applications. - Stéphane Badel; Alexandre Schmid; Yusuf Leblebici (ESANN, 2003)

A VLSI Hamming artificial neural network with k-winner-take-all and k-loser-take-all capability. - Stéphane Badel; Alexandre Schmid; Yusuf Leblebici (IJCNN, 2003)

Full-custom CMOS realization of a high-performance binary sorting engine with linear area-time complexity. - Turan Demirci; Ilhan Hatirnaz; Yusuf Leblebici (ISCAS (5), 2003)

Design and realization of a modular 200 MSample/s 12-bit pipelined A/D converter block using deep-submicron digital CMOS technology. - Zeynep Toprak Deniz; Yusuf Leblebici (ISCAS (1), 2003)

Twisted differential on-chip interconnect architecture for inductive/capacitive crosstalk noise cancellation. - Ilhan Hatirnaz; Yusuf Leblebici (SoC, 2003)

A Highly Fault Tolerant PLA Architecture for Failure-Prone Nanometer CMOS and Novel Quantum Device Technologies. - Alexandre Schmid; Yusuf Leblebici (DFT, 2004)

A 4-channel 2.5Gb/s/channel 66dBΩ inductorless transimpedance amplifier [optical receiver applications]. - Paul Muller; Yusuf Leblebici; Matthew K. Emsley; M. Selim Ünlü (ESSCIRC, 2004)

Low noise MCML prefix adders using 0.18 µm CMOS technology. - Elizabeth J. Brauer; Yusuf Leblebici (Circuits, Signals, and Systems, 2004)

Sub-70 PS full adder IN 0.18 µm CMOS current-mode logic. - Elizabeth J. Brauer; Yusuf Leblebici (Circuits, Signals, and Systems, 2004)

Fault-tolerant PLA-style circuit design for failure-prone nanometer CMOS and quantum device technologies. - Alexandre Schmid; Yusuf Leblebici (IJCNN, 2004)

Mixed analog-digital image processing circuit based on Hamming artificial neural network architecture. - Stéphane Badel; Alexandre Schmid; Yusuf Leblebici (ISCAS (5), 2004)

Modelling and implementation of twisted differential on-chip interconnects for crosstalk noise reduction. - Ilhan Hatirnaz; Yusuf Leblebici (ISCAS (5), 2004)

Robust and fault-tolerant circuit design for nanometer-scale devices and single-electron transistors. - Alexandre Schmid; Yusuf Leblebici (ISCAS (3), 2004)

Providing QoS to connection-less packet-switched NoC by implementing DiffServ functionalities. - Mehmet Derin Harmanci; Nuria Pazos Escudero; Yusuf Leblebici; Paolo Ienne (SoC, 2004)

Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors. - Alexandre Schmid; Yusuf Leblebici (IEEE Trans. Very Large Scale Integr. Syst., 2004)

CONAN - A Design Exploration Framework for Reliable Nano-Electronics. - Sorin Cotofana; Alexandre Schmid; Yusuf Leblebici; Adrian M. Ionescu; Oliver Soffke; Peter Zipf; Manfred Glesner; Antonio Rubio 001 (ASAP, 2005)

Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit. - Paul Muller; Armin Tajalli; Seyed Mojtaba Atarodi; Yusuf Leblebici (DATE, 2005)

A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18μm digital CMOS technology. - Armin Tajalli; Paul Muller; Mojtaba Atarodi; Yusuf Leblebici (ESSCIRC, 2005)

Characterizing and Exploiting Task-Load Variability and Correlation for Energy Management in multi-core systems. - Soner Yaldiz; Alper Demir 001; Serdar Tasiran; Paolo Ienne; Yusuf Leblebici (ESTIMedia, 2005)

Jitter Tolerance Analysis of Clock and Data Recovery Circuits. - Paul Muller; Yusuf Leblebici (FDL, 2005)

Quantitative modelling and comparison of communication schemes to guarantee quality-of-service in networks-on-chip. - Mehmet Derin Harmanci; Nuria Pazos Escudero; Yusuf Leblebici; Paolo Ienne (ISCAS (2), 2005)

Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture. - Takahide Oya; Tetsuya Asai; Yoshihito Amemiya; Alexandre Schmid; Yusuf Leblebici (ISCAS (3), 2005)

Low-power current mode logic for improved DPA-resistance in embedded systems. - Zeynep Toprak Deniz; Yusuf Leblebici (ISCAS (2), 2005)

A low-power, multichannel gated oscillator-based CDR for short-haul applications. - Armin Tajalli; Paul Muller; Seyed Mojtaba Atarodi; Yusuf Leblebici (ISLPED, 2005)

Limiting amplifiers for next-generation multi-channel optical I/0 interfaces in SoCs. - Paul Muller; Yusuf Leblebici (SoCC, 2005)

A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault- Tolerance Analysis. - Milos Stanisavljevic; Alexandre Schmid; Yusuf Leblebici (VLSI-SoC, 2005)

On the fault tolerance of a clustered single-electron neural network for differential enhancement. - Takahide Oya; Alexandre Schmid; Tetsuya Asai; Yusuf Leblebici; Yoshihito Amemiya (IEICE Electron. Express, 2005)

A simulation methodology for reliability analysis in multi-core SoCs. - Ayse K. Coskun; Tajana Simunic Rosing; Yusuf Leblebici; Giovanni De Micheli (ACM Great Lakes Symposium on VLSI, 2006)

Fault-Tolerance of Robust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density. - Milos Stanisavljevic; Alexandre Schmid; Yusuf Leblebici (IJCNN, 2006)

Weak inversion performance of CMOS and DCVSPG logic families in sub-300 mV range. - Omer Can Akgun; Yusuf Leblebici (ISCAS, 2006)

Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design. - Elizabeth J. Brauer; Ilhan Hatirnaz; Stéphane Badel; Yusuf Leblebici (ISCAS, 2006)

Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs. - Armin Tajalli; Paul Muller; Seyed Mojtaba Atarodi; Yusuf Leblebici (ISCAS, 2006)

Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells. - Stéphane Badel; Ilhan Hatirnaz; Yusuf Leblebici; Elizabeth J. Brauer (VLSI-SoC, 2006)

Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation. - Zeynep Toprak Deniz; Yusuf Leblebici; Eric A. Vittoz (VLSI-SoC, 2006)

A Predictable Communication Scheme for Embedded Multiprocessor Systems. - Mehmet Derin Harmanci; Nuria Pazos; Paolo Ienne; Yusuf Leblebici (VLSI-SoC, 2006)

Analysis and Optimization of MPSoC Reliability. - Ayse Kivilcim Coskun; Tajana Simunic; Kresimir Mihic; Giovanni De Micheli; Yusuf Leblebici (J. Low Power Electron., 2006)

Current sensing completion detection for subthreshold asynchronous circuits. - Omer Can Akgun; Yusuf Leblebici; Eric A. Vittoz (ECCTD, 2007)

Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept. - Armin Tajalli; Eric A. Vittoz; Yusuf Leblebici; Elizabeth J. Brauer (ESSCIRC, 2007)

Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density. - Milos Stanisavljevic; Frank K. Gürkaynak; Alexandre Schmid; Yusuf Leblebici; Maria Gabrani (ACM Great Lakes Symposium on VLSI, 2007)

Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays. - M. Haykel Ben Jamaa; Kirsten E. Moselund; David Atienza; Didier Bouvet; Adrian M. Ionescu; Yusuf Leblebici; Giovanni De Micheli (ICCAD, 2007)

Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage. - Stéphane Badel; Yusuf Leblebici (ISCAS, 2007)

A 90nm CMOS cryptographic core with improved fault-tolerance in presence of massive defect density. - Milos Stanisavljevic; Frank Kagan Gürkaynak; Alexandre Schmid; Yusuf Leblebici; Maria Gabrani (Nano-Net, 2007)

A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies. - Francesco Regazzoni 001; Stéphane Badel; Thomas Eisenbarth 001; Johann Großschädl; Axel Poschmann; Zeynep Toprak Deniz; Marco Macchetti; Laura Pozzi 001; Christof Paar; Yusuf Leblebici; Paolo Ienne (ICSAMOS, 2007)

Early wire characterization for predictable network-on-chip global interconnects. - Ilhan Hatirnaz; Stéphane Badel; Nuria Pazos; Yusuf Leblebici; Srinivasan Murali; David Atienza; Giovanni De Micheli (SLIP, 2007)

Predictable system interconnects through accurate early wire characterization. - I. Hatyrnaz; Stéphane Badel; Nuria Pazos; Yusuf Leblebici (SoCC, 2007)

Tradeoffs in Design of Low-Power Gated-Oscillator Clock and Data Recovery Circuits. - Armin Tajalli; Paul Muller; Yusuf Leblebici (J. Low Power Electron., 2007)

On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation. - Zeynep Toprak Deniz; Yusuf Leblebici; Eric A. Vittoz (IEEE J. Solid State Circuits, 2007)

A Power-Efficient Clock and Data Recovery Circuit in 0.18 µm CMOS Technology for Multi-Channel Short-Haul Optical Data Communication. - Armin Tajalli; Paul Muller; Yusuf Leblebici (IEEE J. Solid State Circuits, 2007)

A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18μm CMOS technology. - Thomas Liechti; Armin Tajalli; Omer Can Akgun; Zeynep Toprak Deniz; Yusuf Leblebici (APCCAS, 2008)

Design space exploration for field programmable compressor trees. - Seyed-Hosein Attarzadeh-Niaki; Alessandro Cevrero; Philip Brisk; Chrysostomos Nicopoulos; Frank K. Gürkaynak; Yusuf Leblebici; Paolo Ienne (CASES, 2008)

Programmable logic circuits based on ambipolar CNFET. - M. Haykel Ben Jamaa; David Atienza; Yusuf Leblebici; Giovanni De Micheli (DAC, 2008)

A Generic Standard Cell Design Methodology for Differential Circuit Styles. - Stéphane Badel; Erdem Guleyupoglu; Ozgur Inac; Anna Pena Martinez; Paolo Vietti; Frank K. Gürkaynak; Yusuf Leblebici (DATE, 2008)

Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces. - Carlotta Guiducci; Alexandre Schmid; Frank K. Gürkaynak; Yusuf Leblebici (DATE, 2008)

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. - Alessandro Cevrero; Panagiotis Athanasopoulos; Hadi Parandeh-Afshar; Ajay Kumar Verma; Philip Brisk; Frank K. Gürkaynak; Yusuf Leblebici; Paolo Ienne (FPGA, 2008)

Improving the power-delay product in SCL circuits using source follower output stage. - Armin Tajalli; Frank K. Gürkaynak; Yusuf Leblebici; Massimo Alioto; Elizabeth J. Brauer (ISCAS, 2008)

Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs. - Bahman Kheradmand Boroujeni; Christian Piguet; Yusuf Leblebici (PATMOS, 2008)

Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits. - Armin Tajalli; Massimo Alioto; Elizabeth J. Brauer; Yusuf Leblebici (PATMOS, 2008)

Energy Efficiency Comparison of Asynchronous and Synchronous Circuits Operating in the Sub-Threshold Regime. - Omer Can Akgun; Yusuf Leblebici (J. Low Power Electron., 2008)

Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications. - Armin Tajalli; Elizabeth J. Brauer; Yusuf Leblebici; Eric A. Vittoz (IEEE J. Solid State Circuits, 2008)

CMOS realization of two-dimensional mixed analog-digital Hamming distance discriminator circuits for real-time imaging applications. - Stéphane Badel; Alexandre Schmid; Yusuf Leblebici (Microelectron. J., 2008)

Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories. - M. Haykel Ben Jamaa; Kirsten E. Moselund; David Atienza; Didier Bouvet; Adrian M. Ionescu; Yusuf Leblebici; Giovanni De Micheli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Validation of the porous-medium approach to model interlayer-cooled 3D-chip stacks. - Thomas Brunschwiler; Stephan Paredes; Ute Drechsler; Bruno Michel; W. Cesar; G. Töral; Yuksel Temiz; Yusuf Leblebici (3DIC, 2009)

A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories. - M. Haykel Ben Jamaa; David Atienza; Yusuf Leblebici; Giovanni De Micheli (ASP-DAC, 2009)

Complete nanowire crossbar framework optimized for the multi-spacer patterning technique. - M. Haykel Ben Jamaa; Gianfranco Cerofolini; Yusuf Leblebici; Giovanni De Micheli (CASES, 2009)

A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. - Francesco Regazzoni 001; Alessandro Cevrero; François-Xavier Standaert; Stéphane Badel; Theo Kluter; Philip Brisk; Yusuf Leblebici; Paolo Ienne (CHES, 2009)

A widely-tunable and ultra-low-power MOSFET-C filter operating in subthreshold. - Armin Tajalli; Yusuf Leblebici (CICC, 2009)

Decoding nanowire arrays fabricated with the multi-spacer patterning technique. - M. Haykel Ben Jamaa; Yusuf Leblebici; Giovanni De Micheli (DAC, 2009)

Dynamic thermal management in 3D multicore architectures. - Ayse K. Coskun; José L. Ayala; David Atienza; Tajana Simunic Rosing; Yusuf Leblebici (DATE, 2009)

Optimization of Nanoelectronic Systems Reliability Under Massive Defect Density Using Distributed R-fold Modular Redundancy (DRMR). - Milos Stanisavljevic; Alexandre Schmid; Yusuf Leblebici (DFT, 2009)

A micropower neural recording amplifier with improved noise efficiency factor. - Vahid Majidzadeh; Alexandre Schmid; Yusuf Leblebici (ECCTD, 2009)

A fully on-chip LDO voltage regulator for remotely powered cortical implants. - Vahid Majidzadeh; Alexandre Schmid; Yusuf Leblebici (ESSCIRC, 2009)

Subthreshold SCL for ultra-low-power SRAM and low-activity-rate digital systems. - Armin Tajalli; Yusuf Leblebici (ESSCIRC, 2009)

3D configuration caching for 2D FPGAs. - Alessandro Cevrero; Panagiotis Athanasopoulos; Hadi Parandeh-Afshar; Philip Brisk; Yusuf Leblebici; Paolo Ienne; Maurizio Skerlj (FPGA, 2009)

Using 3D integration technology to realize multi-context FPGAs. - Alessandro Cevrero; Panagiotis Athanasopoulos; Hadi Parandeh-Afshar; Maurizio Skerlj; Philip Brisk; Yusuf Leblebici; Paolo Ienne (FPL, 2009)

A flexible DSP block to enhance FPGA arithmetic performance. - Hadi Parandeh-Afshar; Alessandro Cevrero; Panagiotis Athanasopoulos; Philip Brisk; Yusuf Leblebici; Paolo Ienne (FPT, 2009)

CMOS compressed imaging by Random Convolution. - Laurent Jacques; Pierre Vandergheynst; Alexandre Bibet; Vahid Majidzadeh; Alexandre Schmid; Yusuf Leblebici (ICASSP, 2009)

Memory organization and data layout for instruction set extensions with architecturally visible storage. - Panagiotis Athanasopoulos; Philip Brisk; Yusuf Leblebici; Paolo Ienne (ICCAD, 2009)

A pulse-density modulation circuit exhibiting noise shaping with single-electron neurons. - Andrew Kilinga Kikombo; Tetsuya Asai; Takahide Oya; Alexandre Schmid; Yusuf Leblebici; Yoshihito Amemiya (IJCNN, 2009)

Optimization of Wire Grid Size for Differential Routing and Impact on the Power-delay-area Tradeoff. - Massimo Alioto; Stéphane Badel; Yusuf Leblebici (ISCAS, 2009)

Analysis and Design of Ultra-low Power Subthreshold MCML Gates. - Massimo Alioto; Yusuf Leblebici (ISCAS, 2009)

Load Optimization of an Inductive Power Link for Remote Powering of Biomedical Implants. - Kanber Mithat Silay; Denis Dondi; Luca Larcher; Michel J. Declercq; Luca Benini; Yusuf Leblebici; Catherine Dehollain (ISCAS, 2009)

Subthreshold Leakage Reduction: A Comparative Study of SCL and CMOS Design. - Armin Tajalli; Yusuf Leblebici (ISCAS, 2009)

Through Silicon Via-Based Grid for Thermal Control in 3D Chips. - José L. Ayala; Arvind Sridhar; Vinod Pangracious; David Atienza; Yusuf Leblebici (NanoNet, 2009)

Optimization of Nanoelectronic Systems Reliability by Reducing Logic Depth. - Milos Stanisavljevic; Alexandre Schmid; Yusuf Leblebici (NanoNet, 2009)

Subthreshold Circuit Design for Ultra-Low-Power Applications. - Yusuf Leblebici (PATMOS, 2009)

Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-Vt Domain By Architectural Folding. - Joachim Neves Rodrigues; Omer Can Akgun; Puneet Acharya; Adolfo de la Calle; Yusuf Leblebici; Viktor Öwall (PATMOS, 2009)

A current sensing completion detection method for asynchronous pipelines operating in the sub-threshold regime. - Omer Can Akgun; Frank K. Gürkaynak; Yusuf Leblebici (Int. J. Circuit Theory Appl., 2009)

A Neuromorphic Single-Electron Circuit for Noise-Shaping Pulse-Density Modulation. - Andrew Kilinga Kikombo; Tetsuya Asai; Takahide Oya; Alexandre Schmid; Yusuf Leblebici (Int. J. Nanotechnol. Mol. Comput., 2009)

On the Reliability of Post-CMOS and SET Systems. - Milos Stanisavljevic; Alexandre Schmid; Yusuf Leblebici (Int. J. Nanotechnol. Mol. Comput., 2009)

Electrical modeling of the cell-electrode interface for recording neural activity from high-density microelectrode arrays. - Neil Joye; Alexandre Schmid; Yusuf Leblebici (Neurocomputing, 2009)

A Slew Controlled LVDS Output Driver Circuit in 0.18 µm CMOS Technology. - Armin Tajalli; Yusuf Leblebici (IEEE J. Solid State Circuits, 2009)

Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5 fJ/stage PDP. - Armin Tajalli; Elizabeth J. Brauer; Yusuf Leblebici (Microelectron. J., 2009)

Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits. - Armin Tajalli; Massimo Alioto; Yusuf Leblebici (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Leakage Current Reduction Using Subthreshold Source-Coupled Logic. - Armin Tajalli; Yusuf Leblebici (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology. - Francesco Regazzoni 001; Thomas Eisenbarth 001; Axel Poschmann; Johann Großschädl; Frank K. Gürkaynak; Marco Macchetti; Zeynep Toprak Deniz; Laura Pozzi 001; Christof Paar; Yusuf Leblebici; Paolo Ienne (Trans. Comput. Sci., 2009)

Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. - Alessandro Cevrero; Panagiotis Athanasopoulos; Hadi Parandeh-Afshar; Ajay Kumar Verma; Seyed-Hosein Attarzadeh-Niaki; Chrysostomos Nicopoulos; Frank K. Gürkaynak; Philip Brisk; Yusuf Leblebici; Paolo Ienne (ACM Trans. Reconfigurable Technol. Syst., 2009)

Integrating bio-sensing functions on CMOS chips. - Carlotta Guiducci; Yuksel Temiz; Yusuf Leblebici; Enrico Accastelli; Anna Ferretti; Giulia Cappi; Elena Bianchi (APCCAS, 2010)

AVGS-Mux style: A novel technology and device independent technique for reducing power and compensating process variations in FPGA fabrics. - Bahman Kheradmand Boroujeni; Christian Piguet; Yusuf Leblebici (DATE, 2010)

Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits. - Armin Tajalli; Yusuf Leblebici (DATE, 2010)

Subthreshold current-mode oscillator-based quantizer with 3-decade scalable sampling rate and pico-Ampere range resolution. - Armin Tajalli; Yusuf Leblebici (ESSCIRC, 2010)

A 9 pW/Hz adjustable clock generator with 3-decade tuning range for dynamic power management in subthreshold SCL systems. - Armin Tajalli; Yusuf Leblebici (ESSCIRC, 2010)

A (256×256) pixel 76.7mW CMOS imager/ compressor based on real-time In-pixel compressive sensing. - Vahid Majidzadeh; Laurent Jacques; Alexandre Schmid; Pierre Vandergheynst; Yusuf Leblebici (ISCAS, 2010)

Memristive devices fabricated with silicon nanowire schottky barrier transistors. - Davide Sacchetto; M. Haykel Ben Jamaa; Sandro Carrara; Giovanni De Micheli; Yusuf Leblebici (ISCAS, 2010)

Design aspects of carry lookahead adders with vertically-stacked nanowire transistors. - Davide Sacchetto; M. Haykel Ben Jamaa; Giovanni De Micheli; Yusuf Leblebici (ISCAS, 2010)

Selective redundancy-based design techniques for the minimization of local delay variations. - Milos Stanisavljevic; Alexandre Schmid; Yusuf Leblebici (ISCAS, 2010)

Logic Architecture and VDD Selection for Reducing the Impact of Intra-die Random VT Variations on Timing. - Bahman Kheradmand Boroujeni; Christian Piguet; Yusuf Leblebici (PATMOS, 2010)

Output probability density functions of logic circuits: Modeling and fault-tolerance evaluation. - Milos Stanisavljevic; Alexandre Schmid; Yusuf Leblebici (VLSI-SoC, 2010)

Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs. - Fengda Sun; Alessandro Cevrero; Panagiotis Athanasopoulos; Yusuf Leblebici (VLSI-SoC, 2010)

Efficient and side-channel-aware implementations of elliptic curve cryptosystems over prime fields. - Deniz Karakoyunlu; Frank Kagan Gürkaynak; Berk Sunar; Yusuf Leblebici (IET Inf. Secur., 2010)

Nanowatt Range Folding-Interpolating Analog-to-Digital Converter Using Subthreshold Source-Coupled Circuits. - Armin Tajalli; Yusuf Leblebici (J. Low Power Electron., 2010)

Optimization of the wire grid size for differential routing: Analysis and impact on the power-delay-area tradeoff. - Massimo Alioto; Stéphane Badel; Yusuf Leblebici (Microelectron. J., 2010)

Capacitance DNA bio-chips improved by new probe immobilization strategies. - Sandro Carrara; Andrea Cavallini 001; Yusuf Leblebici; Giovanni De Micheli; Vijayender Bhalla; Francesco Valle; Bruno Samorì; Luca Benini; Bruno Riccò; Inger Vikholm-Lundin; Tony Munter (Microelectron. J., 2010)

Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library. - Alessandro Cevrero; Francesco Regazzoni 001; Micheal Schwander; Stéphane Badel; Paolo Ienne; Yusuf Leblebici (DAC, 2011)

Towards thermally-aware design of 3D MPSoCs with inter-tier cooling. - Mohamed M. Sabry; Arvind Sridhar; David Atienza; Yuksel Temiz; Yusuf Leblebici; S. Szczukiewicz; Navid Borhani; John Richard Thome; Thomas Brunschwiler; Bruno Michel (DATE, 2011)

Design trade-offs in ultra-low-power CMOS and STSCL digital systems. - Armin Tajalli; Yusuf Leblebici (ECCTD, 2011)

PRO3D, Programming for Future 3D Manycore Architectures: Project's Interim Status. - Christian Fabre; Iuliana Bacivarov; Ananda Basu; Martino Ruggiero; David Atienza; Eric Flamand; Jean-Pierre Krimm; Julien Mottin; Lars Schor; Pratyush Kumar; Hoeseok Yang; Devesh B. Chokshi; et al. (FMCO, 2011)

Hardware security in VLSI. - Wayne P. Burleson; Yusuf Leblebici (ACM Great Lakes Symposium on VLSI, 2011)

Alternative design methodologies for the next generation logic switch. - Davide Sacchetto; Michele De Marchi; Giovanni De Micheli; Yusuf Leblebici (ICCAD, 2011)

Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders. - Christoph Roth; Alessandro Cevrero; Christoph Studer; Yusuf Leblebici; Andreas Burg 001 (ISCAS, 2011)

Amplitude modulation based readout for very dense active microelectrode arrays. - Neil Joye; Alexandre Schmid; Yusuf Leblebici (IEICE Electron. Express, 2011)

Optimal Logic Architecture and Supply Voltage Selection Method to Reduce the Impact of the Threshold Voltage Variation on the Timing. - Bahman Kheradmand Boroujeni; Christian Piguet; Yusuf Leblebici (J. Low Power Electron., 2011)

Energy Efficient Low-Noise Neural Recording Amplifier With Enhanced Noise Efficiency Factor. - Vahid Majidzadeh; Alexandre Schmid; Yusuf Leblebici (IEEE Trans. Biomed. Circuits Syst., 2011)

Design Trade-offs in Ultra-Low-Power Digital Nanoscale CMOS. - Armin Tajalli; Yusuf Leblebici (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Low-Power and Widely Tunable Linearized Biquadratic Low-Pass Transconductor-C Filter. - Armin Tajalli; Yusuf Leblebici (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors. - Shashikanth Bobba; Michele De Marchi; Yusuf Leblebici; Giovanni De Micheli (DAC, 2012)

Design and Implementation of Multi-camera Systems Distributed over a Spherical Geometry. - Hossein Afshari; Kerem Seyid; Alexandre Schmid; Yusuf Leblebici (Diagrams, 2012)

Enhanced Omnidirectional Image Reconstruction Algorithm and Its Real-Time Hardware. - Abdulkadir Akin; Elif Erdede; Hossein Afshari; Alexandre Schmid; Yusuf Leblebici (DSD, 2012)

Design techniques and analysis of high-resolution neural recording systems targeting epilepsy focus localization. - Mahsa Shoaran; Claudio Pollo; Yusuf Leblebici; Alexandre Schmid (EMBC, 2012)

Quantitative comparison of commercial CCD and custom-designed CMOS camera for biological applications. - Gozen Koklu; Julien Ghaye; Rene Beuchat; Giovanni De Micheli; Yusuf Leblebici; Sandro Carrara (ISCAS, 2012)

Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors. - Shashikanth Bobba; Pierre-Emmanuel Gaillardon; Jian Zhang 067; Michele De Marchi; Davide Sacchetto; Yusuf Leblebici; Giovanni De Micheli (NANOARCH, 2012)

Real-Time FPGA Implementation of Linear Blending Vision Reconstruction Algorithm Using a Spherical Light Field Camera. - Hossein Afshari; Abdulkadir Akin; Vladan Popovic; Alexandre Schmid; Yusuf Leblebici (SiPS, 2012)

3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory. - Giulia Beanato; Igor Loi; Giovanni De Micheli; Yusuf Leblebici; Luca Benini (VLSI-SoC, 2012)

Configurable Low-Latency Interconnect for Multi-core Clusters. - Giulia Beanato; Igor Loi; Giovanni De Micheli; Yusuf Leblebici; Luca Benini (VLSI-SoC (Selected Papers), 2012)

GMS: Generic memristive structure for non-volatile FPGAs. - Pierre-Emmanuel Gaillardon; Davide Sacchetto; Shashikanth Bobba; Yusuf Leblebici; Giovanni De Micheli (VLSI-SoC, 2012)

An 8-PPM, 45 pJ/bit UWB transmitter with reduced number of PA elements. - Vahid Majidzadeh; Alexandre Schmid; Yusuf Leblebici; Jan M. Rabaey (VLSIC, 2012)

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology. - Giulia Beanato; Paolo Giovannini; Alessandro Cevrero; Panagiotis Athanasopoulos; Michael Zervas; Yuksel Temiz; Yusuf Leblebici (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review. - Davide Sacchetto; Giovanni De Micheli; Yusuf Leblebici (Proc. IEEE, 2012)

High-Level Energy Estimation in the Sub-V$_{{ rm T}}$ Domain: Simulation and Measurement of a Cardiac Event Detector. - Omer Can Akgun; Joachim Neves Rodrigues; Yusuf Leblebici; Viktor Öwall (IEEE Trans. Biomed. Circuits Syst., 2012)

Wide-Range Dynamic Power Management in Low-Voltage Low-Power Subthreshold SCL. - Armin Tajalli; Yusuf Leblebici (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A spherical multi-camera system with real-time omnidirectional video acquisition capability. - Hossein Afshari; Vladan Popovic; Tugce Tasci; Alexandre Schmid; Yusuf Leblebici (IEEE Trans. Consumer Electron., 2012)

Integration of intra chip stack fluidic cooling using thin-layer solder bonding. - Yassir Madhour; Michael Zervas; Gerd Schlottig; Thomas Brunschwiler; Yusuf Leblebici; John Richard Thome; Bruno Michel (3DIC, 2013)

FireBird: PowerPC e200 based SoC for high temperature operation. - Radisav Cojbasic; Omer Cogal; Pascal Andreas Meinerzhagen; Christian Senning; Conor Slater; Thomas Maeder; Andreas Burg 001; Yusuf Leblebici (CICC, 2013)

A 16-channel, 359 μW, parallel neural recording system using Walsh-Hadamard coding. - Vahid Majidzadeh; Alexandre Schmid; Yusuf Leblebici (CICC, 2013)

Towards structured ASICs using polarity-tunable Si nanowire transistors. - Pierre-Emmanuel Gaillardon; Michele De Marchi; Luca Gaetano Amarù; Shashikanth Bobba; Davide Sacchetto; Yusuf Leblebici; Giovanni De Micheli (DAC, 2013)

Fast and accurate BER estimation methodology for I/O links based on extreme value theory. - Alessandro Cevrero; Nestor E. Evmorfopoulos; Charalampos Antoniadis; Paolo Ienne; Yusuf Leblebici; Andreas Burg 001; Georgios I. Stamoulis (DATE, 2013)

Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs. - Pierre-Emmanuel Gaillardon; Luca Gaetano Amarù; Shashikanth Bobba; Michele De Marchi; Davide Sacchetto; Yusuf Leblebici; Giovanni De Micheli (DATE, 2013)

3D-MMC: a modular 3D multi-core architecture with efficient resource pooling. - Tiansheng Zhang; Alessandro Cevrero; Giulia Beanato; Panagiotis Athanasopoulos; Ayse K. Coskun; Yusuf Leblebici (DATE, 2013)

Interconnected network of cameras. - Mahdad Hosseini Kamal; Hossein Afshari; Yusuf Leblebici; Alexandre Schmid; Pierre Vandergheynst (Sensors, Cameras, and Systems for Industrial and Scientific Applications, 2013)

A hardware-oriented dynamically adaptive disparity estimation algorithm and its real-time hardware. - Abdulkadir Akin; Ipek Baz; Baris Atakan; Irem Boybat; Alexandre Schmid; Yusuf Leblebici (ACM Great Lakes Symposium on VLSI, 2013)

High frame-rate low-power compressive sampling CMOS image sensor architecture: [extended abstract]. - Nikola Katic; Mahdad Hosseini Kamal; Mustafa Kilic; Alexandre Schmid; Pierre Vandergheynst; Yusuf Leblebici (ACM Great Lakes Symposium on VLSI, 2013)

Compressive multichannel cortical signal recording. - Mahdad Hosseini Kamal; Mahsa Shoaran; Yusuf Leblebici; Alexandre Schmid; Pierre Vandergheynst (ICASSP, 2013)

Real-time hardware implementation of multi-resolution image blending. - Vladan Popovic; Kerem Seyid; Alexandre Schmid; Yusuf Leblebici (ICASSP, 2013)

Characterization of standard CMOS compatible photodiodes and pixels for Lab-on-Chip devices. - Gozen Koklu; Ralph Etienne-Cummings; Yusuf Leblebici; Giovanni De Micheli; Sandro Carrara (ISCAS, 2013)

A low-power area-efficient compressive sensing approach for multi-channel neural recording. - Mahsa Shoaran; Mariazel Maqueda Lopez; Vijaya Sankara Rao Pasupureddi; Yusuf Leblebici; Alexandre Schmid (ISCAS, 2013)

Spherical Panorama Construction Using Multi Sensor Registration Priors and Its Real-Time Hardware. - Omer Cogal; Vladan Popovic; Yusuf Leblebici (ISM, 2013)

A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS. - Lukas Kull; Thomas Toifl; Martin L. Schmatz; Pier Andrea Francese; Christian Menolfi; Matthias Braendli; Marcel A. Kossel; Thomas Morf; Toke Meyer Andersen; Yusuf Leblebici (ISSCC, 2013)

Power-efficient CMOS image acquisition system based on compressive sampling. - Nikola Katic; Mahdad Hosseini Kamal; Mustafa Kilic; Alexandre Schmid; Pierre Vandergheynst; Yusuf Leblebici (MWSCAS, 2013)

Column-separated compressive sampling scheme for low power CMOS image sensors. - Nikola Katic; Mahdad Hosseini Kamal; Mustafa Kilic; Alexandre Schmid; Pierre Vandergheynst; Yusuf Leblebici (NEWCAS, 2013)

Compressed look-up-table based real-time rectification hardware. - Abdulkadir Akin; Ipek Baz; Luis Manuel Gaemperle; Alexandre Schmid; Yusuf Leblebici (VLSI-SoC, 2013)

Enhanced Compressed Look-up-Table Based Real-Time Rectification Hardware. - Abdulkadir Akin; Luis Manuel Gaemperle; Halima Najibi; Alexandre Schmid; Yusuf Leblebici (VLSI-SoC (Selected Papers), 2013)

Hemispherical Multiple Camera System for High Resolution Omni-Directional Light Field Imaging. - Abdulkadir Akin; Omer Cogal; Kerem Seyid; Hossein Afshari; Alexandre Schmid; Yusuf Leblebici (IEEE J. Emerg. Sel. Topics Circuits Syst., 2013)

A Scalable and Adaptive Technique for Compensating Process Variations and Controlling Leakage and Delay in the FPGA. - Bahman Kheradmand Boroujeni; Christian Piguet; Yusuf Leblebici (J. Low Power Electron., 2013)

A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS. - Lukas Kull; Thomas Toifl; Martin L. Schmatz; Pier Andrea Francese; Christian Menolfi; Matthias Braendli; Marcel A. Kossel; Thomas Morf; Toke Meyer Andersen; Yusuf Leblebici (IEEE J. Solid State Circuits, 2013)

The PANOPTIC Camera: A Plenoptic Sensor with Real-Time Omnidirectional Capability. - Hossein Afshari; Laurent Jacques; Luigi Bagnato; Alexandre Schmid; Pierre Vandergheynst; Yusuf Leblebici (J. Signal Process. Syst., 2013)

A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS. - Lukas Kull; Jan Plíva; Thomas Toifl; Martin L. Schmatz; Pier Andrea Francese; Christian Menolfi; Matthias Braendli; Marcel A. Kossel; Thomas Morf; Toke Meyer Andersen; Yusuf Leblebici (A-SSCC, 2014)

Programmable active pixel sensor for low-light biomedical applications. - Gozen Koklu; Yusuf Leblebici; Giovanni De Micheli; Sandro Carrara (BioCAS, 2014)

3D serial TSV link for low-power chip-to-chip communication. - Giulia Beanato; Alessandro Cevrero; Giovanni De Micheli; Yusuf Leblebici (ICICDT, 2014)

An Immersive Telepresence System Using a Real-Time Omnidirectional Camera and a Virtual Reality Head-Mounted Display. - Luis Manuel Gaemperle; Kerem Seyid; Vladan Popovic; Yusuf Leblebici (ISM, 2014)

22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS. - Lukas Kull; Thomas Toifl; Martin L. Schmatz; Pier Andrea Francese; Christian Menolfi; Matthias Braendli; Marcel A. Kossel; Thomas Morf; Toke Meyer Andersen; Yusuf Leblebici (ISSCC, 2014)

Parallel vs. serial inter-plane communication using TSVs. - Somayyeh Rahimian Omam; Yusuf Leblebici; Giovanni De Micheli (LASCAS, 2014)

A retina-inspired robust on-focal-plane multi-band edge-detection scheme for CMOS image sensors. - Nikola Katic; Alexandre Schmid; Yusuf Leblebici (MWSCAS, 2014)

A 5.43-μW 0.8-V subthreshold current-sensing ΣΔ modulator for low-noise sensor interfaces. - Nikola Katic; Ibrahim Kazi; Armin Tajalli; Alexandre Schmid; Yusuf Leblebici (NORCHIP, 2014)

Reconfigurable forward homography estimation system for real-time applications. - Vladan Popovic; Yusuf Leblebici (VLSI-SoC, 2014)

Real-Time Omnidirectional Imaging System with Interconnected Network of Cameras. - Kerem Seyid; Ömer Çogal; Vladan Popovic; Hossein Afshari; Alexandre Schmid; Yusuf Leblebici (VLSI-SoC (Selected Papers), 2014)

Dynamically adaptive real-time disparity estimation hardware using iterative refinement. - Abdulkadir Akin; Ipek Baz; Alexandre Schmid; Yusuf Leblebici (Integr., 2014)

Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design. - Ibrahim Kazi; Pascal Andreas Meinerzhagen; Pierre-Emmanuel Gaillardon; Davide Sacchetto; Yusuf Leblebici; Andreas Peter Burg; Giovanni De Micheli (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Performance Optimization and FPGA Implementation of Real-Time Tone Mapping. - Vladan Popovic; Eliéva Pignat; Yusuf Leblebici (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Image Blending in a High Frame Rate FPGA-based Multi-Camera System. - Vladan Popovic; Kerem Seyid; Abdulkadir Akin; Ömer Çogal; Hossein Afshari; Alexandre Schmid; Yusuf Leblebici (J. Signal Process. Syst., 2014)

Structured sampling and recovery of iEEG signals. - Luca Baldassarre; Cosimo Aprile; Mahsa Shoaran; Yusuf Leblebici; Volkan Cevher (CAMSAP, 2015)

A ultra-low-power FPGA based on monolithically integrated RRAMs. - Pierre-Emmanuel Gaillardon; Xifan Tang; Jury Sandrini; Maxime Thammasack; Somayyeh Rahimian Omam; Davide Sacchetto; Yusuf Leblebici; Giovanni De Micheli (DATE, 2015)

A novel hybrid architecture for real-time omnidirectional image reconstruction. - Selman Ergünay; Vladan Popovic; Kerem Seyid; Yusuf Leblebici (ICDSC, 2015)

A low-power 490 mpixels/s hardware accelerator for pyramidal decomposition of images. - Vladan Popovic; Yusuf Leblebici (ICIP, 2015)

Live demonstration: Real-time free viewpoint synthesis using three-camera disparity estimation hardware. - Abdulkadir Akin; Raffaele Capoccia; Jonathan Narinx; Jonathan Masur; Alexandre Schmid; Yusuf Leblebici (ISCAS, 2015)

Real-time free viewpoint synthesis using three-camera disparity estimation hardware. - Abdulkadir Akin; Raffaele Capoccia; Jonathan Narinx; Jonathan Masur; Alexandre Schmid; Yusuf Leblebici (ISCAS, 2015)

Design of high-temperature SRAM for reliable operation beyond 250°C. - Radisav Cojbasic; Yusuf Leblebici (ISCAS, 2015)

Low-voltage read/write circuit design for transistorless ReRAM crossbar arrays in 180nm CMOS technology. - Jury Sandrini; Tugba Demirci; Maxime Thammasack; Davide Sacchetto; Yusuf Leblebici (ISCAS, 2015)

Jitter analysis and measurement in subthreshold source-coupled differential ring oscillators. - Mahsa Shoaran; Armin Tajalli; Massimo Alioto; Yusuf Leblebici (ISCAS, 2015)

10.3 A 7.5mW 7.5Gb/s mixed NRZ/multi-tone serial-data transceiver for multi-drop memory interfaces in 40nm CMOS. - Kiarash Gharibdoust; Armin Tajalli; Yusuf Leblebici (ISSCC, 2015)

3.6 GHz CMOS ring oscillator with low tune voltage sensitivity and temperature compensation. - Hasene Gulperi Ozsema; Tugba Demirci; Yusuf Leblebici (NORCAS, 2015)

Full swing 20 GHz frequency divider with 1 V supply voltage in FD-SOI 28 nm technology. - Hasene Gulperi Ozsema; Duygu Kostak; Tugba Demirci; Yusuf Leblebici (NORCAS, 2015)

FIR filters for hardware-based real-time multi-band image blending. - Vladan Popovic; Yusuf Leblebici (Real-Time Image and Video Processing, 2015)

Trinocular adaptive window size disparity estimation algorithm and its real-time hardware. - Abdulkadir Akin; Raffaele Capoccia; Jonathan Narinx; Ipek Baz; Alexandre Schmid; Yusuf Leblebici (VLSI-DAT, 2015)

Design optimization of polyphase digital down converters for extremely high frequency wireless communications. - Gain Kim; Raffaele Capoccia; Yusuf Leblebici (VLSI-SoC, 2015)

Hardware implementation of real-time multiple frame super-resolution. - Kerem Seyid; Sebastien Blanc; Yusuf Leblebici (VLSI-SoC, 2015)

A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS. - Alessandro Cevrero; Cosimo Aprile; Pier Andrea Francese; Urs Bapst; Christian Menolfi; Matthias Braendli; Marcel A. Kossel; Thomas Morf; Lukas Kull; Hazar Yueksel; Ilter Oezkaya; Yusuf Leblebici; et al. (VLSIC, 2015)

A 4×9 Gb/s 1 pJ/b NRZ/multi-tone serial-data transceiver with crosstalk reduction architecture for multi-drop memory interfaces in 40nm CMOS. - Kiarash Gharibdoust; Armin Tajalli; Yusuf Leblebici (VLSIC, 2015)

Compressive image acquisition in modern CMOS IC design. - Nikola Katic; Mahdad Hosseini Kamal; Alexandre Schmid; Pierre Vandergheynst; Yusuf Leblebici (Int. J. Circuit Theory Appl., 2015)

A subthreshold current-sensing ΣΔ modulator for low-voltage and low-power sensor interfaces. - Nikola Katic; Ibrahim Kazi; Armin Tajalli; Alexandre Schmid; Yusuf Leblebici (Int. J. Circuit Theory Appl., 2015)

Hybrid NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces. - Kiarash Gharibdoust; Armin Tajalli; Yusuf Leblebici (IEEE J. Solid State Circuits, 2015)

A sub-mW pulse-based 5-bit flash ADC with a time-domain fully-digital reference ladder. - Nikola Katic; Radisav Cojbasic; Alexandre Schmid; Yusuf Leblebici (Microelectron. J., 2015)

A comparative experimental investigation on responsivity and response speed of photo-diode and photo-BJT structures integrated in a low-cost standard CMOS process. - Nikola Katic; Alexandre Schmid; Yusuf Leblebici (Microelectron. J., 2015)

Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits. - Mahsa Shoaran; Armin Tajalli; Massimo Alioto; Alexandre Schmid; Yusuf Leblebici (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A Real-Time Multiaperture Omnidirectional Visual Sensor Based on an Interconnected Network of Smart Cameras. - Kerem Seyid; Vladan Popovic; Omer Cogal; Abdulkadir Akin; Hossein Afshari; Alexandre Schmid; Yusuf Leblebici (IEEE Trans. Circuits Syst. Video Technol., 2015)

Copper TSV-based die-level via-last 3D integration process with parylene-C adhesive bonding technique. - S. E. Kucuk Eroglu; W. Y. Choo; Yusuf Leblebici (3DIC, 2016)

Architectural modeling of a multi-tone/single-sideband serial link transceiver for lossy wireline data links. - Gain Kim; Yusuf Leblebici (APCCAS, 2016)

Large-scale neural networks implemented with Non-Volatile Memory as the synaptic weight element: Impact of conductance response. - Severin Sidler; Irem Boybat; Robert M. Shelby; Pritish Narayanan; Jun-Woo Jang; Alessandro Fumarola; Kibong Moon; Yusuf Leblebici; Hyunsang Hwang; Geoffrey W. Burr (ESSDERC, 2016)

Learning-Based Near-Optimal Area-Power Trade-offs in Hardware Design for Neural Signal Acquisition. - Cosimo Aprile; Luca Baldassarre; Vipul Gupta; Juhwan Yoo; Mahsa Shoaran; Yusuf Leblebici; Volkan Cevher (ACM Great Lakes Symposium on VLSI, 2016)

Design and Implementation of Real-Time Multi-sensor Vision Systems. - Yusuf Leblebici (ACM Great Lakes Symposium on VLSI, 2016)

A fully-digital spectrum shaping signaling for serial-data transceiver with crosstalk and ISI reduction property in multi-drop memory interfaces. - Kiarash Gharibdoust; Gain Kim; Armin Tajalli; Yusuf Leblebici (ISCAS, 2016)

Block matching based real-time optical flow hardware implementation. - Kerem Seyid; Andrea Richaud; Raffaele Capoccia; Yusuf Leblebici (ISCAS, 2016)

F1: Designing secure systems: Manufacturing, circuits and architectures. - Vivek De; Kerry Bernstein; Takefumi Yoshikawa; Yusuf Leblebici; Marian Verhelst; Mahesh Mehendale; Makoto Nagata (ISSCC, 2016)

A wideband MDLL with jitter reduction scheme for forwarded clock serial links in 40 nm CMOS. - Kiarash Gharibdoust; Armin Tajalli; Yusuf Leblebici (NEWCAS, 2016)

A 16-channel 1.1mm2 implantable seizure control SoC with sub-μW/channel consumption and closed-loop stimulation in 0.18µm CMOS. - Mahsa Shoaran; Masoud Shahshahani; Masoud Farivar; Joyel Almajano; Amirhossein Shahshahani; Alexandre Schmid; Anatol Bragin; Yusuf Leblebici; Azita Emami (VLSI Circuits, 2016)

Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology. - Jury Sandrini; Marios Barlas; Maxime Thammasack; Tugba Demirci; Michele De Marchi; Davide Sacchetto; Pierre-Emmanuel Gaillardon; Giovanni De Micheli; Yusuf Leblebici (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

Review of advances in neural networks: Neural design technology stack. - Adela-Diana Almasi; Stanislaw Wozniak; Valentin Cristea; Yusuf Leblebici; Ton Engbersen (Neurocomputing, 2016)

Multi-camera platform for panoramic real-time HDR video construction and rendering. - Vladan Popovic; Kerem Seyid; Eliéva Pignat; Ömer Çogal; Yusuf Leblebici (J. Real Time Image Process., 2016)

A 4×9 Gb/s 1pJ/b Hybrid NRZ/Multi-Tone I/O With Crosstalk and ISI Reduction for Dense Interconnects. - Kiarash Gharibdoust; Armin Tajalli; Yusuf Leblebici (IEEE J. Solid State Circuits, 2016)

Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS. - Lukas Kull; Jan Plíva; Thomas Toifl; Martin L. Schmatz; Pier Andrea Francese; Christian Menolfi; Matthias Braendli; Marcel A. Kossel; Thomas Morf; Toke Meyer Andersen; Yusuf Leblebici (IEEE J. Solid State Circuits, 2016)

Impact of data serialization over TSVs on routing congestion in 3D-stacked multi-core processors. - Giulia Beanato; Alessandro Cevrero; Giovanni De Micheli; Yusuf Leblebici (Microelectron. J., 2016)

Design and analysis of jitter-aware low-power and high-speed TSV link for 3D ICs. - Giulia Beanato; Kiarash Gharibdoust; Alessandro Cevrero; Giovanni De Micheli; Yusuf Leblebici (Microelectron. J., 2016)

A Digital Spectrum Shaping Signaling Serial-Data Transceiver With Crosstalk and ISI Reduction Property in Multidrop Interfaces. - Gain Kim; Kiarash Gharibdoust; Armin Tajalli; Yusuf Leblebici (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

DCT Learning-Based Hardware Design for Neural Signal Acquisition Systems. - Cosimo Aprile; Johannes Wüthrich; Luca Baldassarre; Yusuf Leblebici; Volkan Cevher (Conf. Computing Frontiers, 2017)

Evolution of oxygen vacancies under electrical characterization for HfOx-based ReRAMs. - B. Attarimashalkoubeh; Jury Sandrini; Elmira Shahrabi; Yusuf Leblebici (ESSDERC, 2017)

Unsupervised Learning Using Phase-Change Synapses and Complementary Patterns. - Severin Sidler; Angeliki Pantazi; Stanislaw Wozniak; Yusuf Leblebici; Evangelos Eleftheriou (ICANN (1), 2017)

Improved Deep Neural Network Hardware-Accelerators Based on Non-Volatile-Memory: The Local Gains Technique. - Irem Boybat; Carmelo di Nolfo; Stefano Ambrogio; Martina Bodini; Nathan C. P. Farinha; Robert M. Shelby; Pritish Narayanan; Severin Sidler; Hsinyu Tsai; Yusuf Leblebici; Geoffrey W. Burr (ICRC, 2017)

Feature Learning Using Synaptic Competition in a Dynamically-Sized Neuromorphic Architecture. - Stanislaw Wozniak; Angeliki Pantazi; Yusuf Leblebici; Evangelos Eleftheriou (ICRC, 2017)

Neuromorphic system with phase-change synapses for pattern learning and feature extraction. - Stanislaw Wozniak; Angeliki Pantazi; Yusuf Leblebici; Evangelos Eleftheriou (IJCNN, 2017)

Reducing circuit design complexity for neuromorphic machine learning systems based on Non-Volatile Memory arrays. - Pritish Narayanan; Lucas L. Sanches; Alessandro Fumarola; Robert M. Shelby; Stefano Ambrogio; Jun-Woo Jang; Hyunsang Hwang; Yusuf Leblebici; Geoffrey W. Burr (ISCAS, 2017)

29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET. - Alessandro Cevrero; Ilter Özkaya; Pier Andrea Francese; Christian Menolfi; Thomas Morf; Matthias Braendli; Daniel M. Kuchta; Lukas Kull; Jonathan E. Proesel; Marcel A. Kossel; Danny Luu; Benjamin G. Lee; et al. (ISSCC, 2017)

Piezoresistivity characterization of silicon nanowires through monolithic MEMS. - Mohammad Nasr Esfahani; Yusuf Leblebici; B. Erdem Alaca (NEMS, 2017)

A hybrid CDAC - threshold configuring SAR ADC in 28nm FDSOI CMOS. - Themistoklis G. Mavrogordatos; Mustafa Kilic; Yusuf Leblebici (NEWCAS, 2017)

An efficient synaptic architecture for artificial neural networks. - Irem Boybat; Manuel Le Gallo; S. R. Nandakumar; Timoleon Moraitis; Tomas Tuma; Bipin Rajendran; Yusuf Leblebici; Abu Sebastian; Evangelos Eleftheriou (NVMTS, 2017)

Neuromorphic computing with multi-memristive synapses. - Irem Boybat; Manuel Le Gallo; S. R. Nandakumar; Timoleon Moraitis; Thomas P. Parnell; Tomas Tuma; Bipin Rajendran; Yusuf Leblebici; Abu Sebastian; Evangelos Eleftheriou (CoRR, 2017)

Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies. - Can Baltaci; Yusuf Leblebici (Integr., 2017)

A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET. - Ilter Özkaya; Alessandro Cevrero; Pier Andrea Francese; Christian Menolfi; Thomas Morf; Matthias Braendli; Daniel M. Kuchta; Lukas Kull; Christian W. Baks; Jonathan E. Proesel; Marcel A. Kossel; Danny Luu; et al. (IEEE J. Solid State Circuits, 2017)

An Insect Eye Inspired Miniaturized Multi-Camera System for Endoscopic Imaging. - Omer Cogal; Yusuf Leblebici (IEEE Trans. Biomed. Circuits Syst., 2017)

Design and Modeling of Serial Data Transceiver Architecture by Employing Multi-Tone Single-Sideband Signaling Scheme. - Gain Kim; Thierry Barailler; Chen Cao; Kiarash Gharibdoust; Yusuf Leblebici (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links. - Gain Kim; Chen Cao; Kiarash Gharibdoust; Armin Tajalli; Yusuf Leblebici (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Neuromorphic Architecture With 1M Memristive Synapses for Detection of Weakly Correlated Inputs. - Stanislaw Wozniak; Angeliki Pantazi; Severin Sidler; Nikolaos Papandreou; Yusuf Leblebici; Evangelos Eleftheriou (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

An area and power efficient on-the-fly LBCS transformation for implantable neuronal signal acquisition systems. - Cosimo Aprile; Johannes Wüthrich; Luca Baldassarre; Yusuf Leblebici; Volkan Cevher (CF, 2018)

Online Feature Learning from a non-i.i.d. Stream in a Neuromorphic System with Synaptic Competition. - Stanislaw Wozniak; Angeliki Pantazi; Yusuf Leblebici; Evangelos Eleftheriou (IJCNN, 2018)

Hardware Implementation of a Smart Camera with Keypoint Detection and Description. - Selman Ergünay; Yusuf Leblebici (ISCAS, 2018)

Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver. - Gain Kim; Lukas Kull; Danny Luu; Matthias Braendli; Christian Menolfi; Pier Andrea Francese; Cosimo Aprile; Thomas Morf; Marcel A. Kossel; Alessandro Cevrero; Ilter Özkaya; Thomas Toifl; et al. (ISCAS, 2018)

A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS. - Ilter Özkaya; Alessandro Cevrero; Pier Andrea Francese; Christian Menolfi; Matthias Braendli; Thomas Morf; Daniel M. Kuchta; Lukas Kull; Marcel A. Kossel; Danny Luu; Mounir Meghelli; Yusuf Leblebici; et al. (ISSCC, 2018)

A Pipelined Speed Enhancement Technique for CDAC-Threshold Configuring SAR ADC. - Mustafa Kilic; Yusuf Leblebici (NEWCAS, 2018)

A 10b SAR ADC with Widely Scalable Sampling Rate and AGC Amplifier Front-End. - Ayca Akkaya; Firat Celik; Armin Tajalli; Yusuf Leblebici (NORCAS, 2018)

A Row-Column Accessed Dynamic Element Matching DAC Architecture for SAR ADCs. - Mustafa Kilic; Selman Ergünay; Yusuf Leblebici (NORCAS, 2018)

Impact of conductance drift on multi-PCM synaptic architectures. - Irem Boybat; S. R. Nandakumar; Manuel Le Gallo; Bipin Rajendran; Yusuf Leblebici; Abu Sebastian; Evangelos Eleftheriou (NVMTS, 2018)

System Level simulation framework for the ASICs development of a novel particle physics detector. - Alessandro Caratelli; Simone Scarfi; Davide Ceresa; Kostas Kloukinas; Yusuf Leblebici (PRIME, 2018)

The key impact of incorporated Al2O3 barrier layer on W-based ReRAM switching performance. - Elmira Shahrabi; Cecilia Giovinazzo; Jury Sandrini; Yusuf Leblebici (PRIME, 2018)

Generalization of Referenceless Timing Mismatch Calibration Methods for Time-Interleaved ADCs. - Arda Uran; Mustafa Kilic; Yusuf Leblebici (PRIME, 2018)

Direct Reconstruction of Saturated Samples in Band-Limited OFDM Signals. - Kyong Hwan Jin; Gain Kim; Yusuf Leblebici; Jong Chul Ye; Michael Unser (CoRR, 2018)

An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels. - Cosimo Aprile; Alessandro Cevrero; Pier Andrea Francese; Christian Menolfi; Matthias Braendli; Marcel A. Kossel; Thomas Morf; Lukas Kull; Ilter Oezkaya; Yusuf Leblebici; Volkan Cevher; Thomas Toifl (IEEE J. Solid State Circuits, 2018)

A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET. - Ilter Özkaya; Alessandro Cevrero; Pier Andrea Francese; Christian Menolfi; Thomas Morf; Matthias Braendli; Daniel M. Kuchta; Lukas Kull; Christian W. Baks; Jonathan E. Proesel; Marcel A. Kossel; Danny Luu; et al. (IEEE J. Solid State Circuits, 2018)

Adaptive Learning-Based Compressive Sampling for Low-power Wireless Implants. - Cosimo Aprile; Kerim Türe; Luca Baldassarre; Mahsa Shoaran; Gürkan Yilmaz; Franco Maloberti; Catherine Dehollain; Yusuf Leblebici; Volkan Cevher (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

FPGA-Based Hardware Implementation of Real-Time Optical Flow Calculation. - Kerem Seyid; Andrea Richaud; Raffaele Capoccia; Yusuf Leblebici (IEEE Trans. Circuits Syst. Video Technol., 2018)

Memory Effects in Multi-terminal Solid State Devices and Their Applications. - Davide Sacchetto; Pierre-Emmanuel Gaillardon; Yusuf Leblebici; Giovanni De Micheli (Handbook of Memristor Networks, 2019)

A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET. - Gain Kim; Lukas Kull; Danny Luu; Matthias Braendli; Christian Menolfi; Pier Andrea Francese; Hazar Yueksel; Cosimo Aprile; Thomas Morf; Marcel A. Kossel; Alessandro Cevrero; Ilter Özkaya; et al. (A-SSCC, 2019)

A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications. - Jonathan Narinx; Robert Giterman; Andrea Bonetti; Nicolas Frigerio; Cosimo Aprile; Andreas Burg 001; Yusuf Leblebici (A-SSCC, 2019)

Real-Time Textureless-Region Tolerant High-Resolution Depth Estimation System. - Bilal Demir; Jean-Philippe Thiran; Yusuf Leblebici (DSD, 2019)

Multi-ReRAM Synapses for Artificial Neural Network Training. - Irem Boybat; Cecilia Giovinazzo; Elmira Shahrabi; Igor Krawczuk; Iason Giannopoulos; Christophe Piveteau; Manuel Le Gallo; Carlo Ricciardi; Abu Sebastian; Evangelos Eleftheriou; Yusuf Leblebici (ISCAS, 2019)

A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET. - Gain Kim; Lukas Kull; Danny Luu; Matthias Braendli; Christian Menolfi; Pier Andrea Francese; Hazar Yueksel; Cosimo Aprile; Thomas Morf; Marcel A. Kossel; Alessandro Cevrero; Ilter Özkaya; et al. (ISSCC, 2019)

Design Considerations and Performance Trade-Offs for 56Gb/s Discrete Multi-Tone Electrical Link. - Gain Kim; Woohyun Kwon; Thomas Toifl; Yusuf Leblebici; Hyeon-Min Bae (MWSCAS, 2019)

Novel 3D architecture of 1S1R. - Behnoush Attarimashalkoubeh; Yusuf Leblebici (NANOARCH, 2019)

ISI Sensitivity of PAM Signaling for Very High-Speed Short-Reach Copper Links. - Firat Celik; Ayca Akkaya; Armin Tajalli; Yusuf Leblebici (NEWCAS, 2019)

Self-Calibrated Delay-Based LSB Extraction for Resolution Improvement in SAR ADCs. - Ayca Akkaya; Firat Celik; Yusuf Leblebici (NORCAS, 2019)

Non-filamentary non-volatile memory elements as synapses in neuromorphic systems. - Alessandro Fumarola; Yusuf Leblebici; Pritish Narayanan; Robert M. Shelby; L. L. Sanchez; Geoffrey W. Burr; Kibong Moon; J. Jang; Hyunsang Hwang; Severin Sidler (NVMTS, 2019)

JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS. - Firat Celik; Ayca Akkaya; Armin Tajalli; Andreas Burg 001; Yusuf Leblebici (PRIME, 2019)

Discrete Time Analysis of Phase Detector Timing Nonidealities in Type-I Sub-Sampling PLL. - Duygu Kostak; Yusuf Leblebici (ICECS, 2020)

A Low-Power 9-Bit 222 MS/s Asynchronous SAR ADC in 65 nm CMOS. - Ayca Akkaya; Firat Celik; Yusuf Leblebici (ISCAS, 2020)

Discrete Time Analysis of Phase Detector Linear Range Extension in Sub-Sampling PLL. - Duygu Kostak; Yusuf Leblebici (ISCAS, 2020)

Real-time high-resolution omnidirectional imaging platform for drone detection and tracking. - Bilal Demir; Selman Ergünay; Gokcen Nurlu; Vladan Popovic; Beat Ott; Peter Wellig; Jean-Philippe Thiran; Yusuf Leblebici (J. Real Time Image Process., 2020)

A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET. - Gain Kim; Marcel A. Kossel; Alessandro Cevrero; Ilter Özkaya; Andreas Burg 001; Thomas Toifl; Yusuf Leblebici; Lukas Kull; Danny Luu; Matthias Braendli; Christian Menolfi; Pier Andrea Francese; et al. (IEEE J. Solid State Circuits, 2020)

A 16-Channel Wireless Neural Recording System-on-Chip with CHT Feature Extraction Processor in 65nm CMOS. - Arda Uran; Kerim Türe; Cosimo Aprile; Alix Trouillet; Florian Fallegger; Azita Emami; Stéphanie P. Lacour; Catherine Dehollain; Yusuf Leblebici; Volkan Cevher (CICC, 2021)

A 32 Gb/s PAM-16 TX and ADC-Based RX AFE with 2-tap embedded analog FFE in 28 nm FDSOI. - Firat Celik; Ayca Akkaya; Yusuf Leblebici (Microelectron. J., 2021)

An 8-Bit 800 MS/s Loop-Unrolled SAR ADC With Common-Mode Adaptive Background Offset Calibration in 28 nm FDSOI. - Ayca Akkaya; Firat Celik; Yusuf Leblebici (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 32-Gb/s PAM-4 SST Transmitter With Four-Tap FFE Using High-Impedance Driver in 28-nm FDSOI. - Firat Celik; Ayca Akkaya; Armin Tajalli; Yusuf Leblebici (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A 16-Channel Neural Recording System-on-Chip With CHT Feature Extraction Processor in 65-nm CMOS. - Arda Uran; Kerim Türe; Cosimo Aprile; Alix Trouillet; Florian Fallegger; Emilie C. M. Revol; Azita Emami; Stéphanie P. Lacour; Catherine Dehollain; Yusuf Leblebici; Volkan Cevher (IEEE J. Solid State Circuits, 2022)