Parasitic Inductance Design for Preventing Oscillatory False Triggering of Parallel-Connected GaN-FETs. - Yusuke Hatakenaka; Kazuhiro Umetani; Masataka Ishihara; Eiji Hiraki; Hiroshi Tadano (IECON, 2021)

Feasibility of Parasitic Drain Inductance Design for Minimizing Switching Loss in Bridge Circuits Using GaN-FETs. - Koki Abe; Masataka Ishihara; Yusuke Hatakenaka; Kazuhiro Umetani; Eiji Hiraki (ISIE, 2021)