Hierarchical power distribution and power management scheme for a single chip mobile processor. - Toshihiro Hattori; Takahiro Irita; Masayuki Ito; Eiji Yamamoto; Hisashi Kato; Go Sado; Tetsuhiro Yamada; Kunihiko Nishiyama; Hiroshi Yagi; Takao Koike; Yoshihiko Tsuchihashi; Motoki Higashida; et al. (DAC, 2006)

Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor. - Yusuke Kanno; Hiroyuki Mizuno; Yoshihiko Yasu; Kenji Hirose; Yasuhisa Shimazaki; Tadashi Hoshi; Yujiro Miyairi; Toshifumi Ishii; Tetsuya Yamada; Takahiro Irita; Toshihiro Hattori; Kazumasa Yanagisawa; et al. (ISSCC, 2006)

In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution. - Yusuke Kanno; Yuki Kondoh; Takahiro Irita; Kenji Hirose; Ryo Mori; Yoshihiko Yasu; Shigenobu Komatsu; Hiroyuki Mizuno (IEEE J. Solid State Circuits, 2007)

Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs. - Yusuke Kanno; Hiroyuki Mizuno; Yoshihiko Yasu; Kenji Hirose; Yasuhisa Shimazaki; Tadashi Hoshi; Yujiro Miyairi; Toshifumi Ishii; Tetsuya Yamada; Takahiro Irita; Toshihiro Hattori; Kazumasa Yanagisawa; et al. (IEEE J. Solid State Circuits, 2007)

A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS. - Masafumi Onouchi; Yusuke Kanno; Makoto Saen; Shigenobu Komatsu; Yoshihiko Yasu; Koichiro Ishibashi (IEEE J. Solid State Circuits, 2010)

Comprehensive electrochemical imaging with local redox cycling-based electrochemical chip device for evaluation of three-dimensional culture cells. - Kosuke Ino; Mustafa Sen; Taku Nishijo; Yusuke Kanno; Hitoshi Shiku; Tomokazu Matsue (MHS, 2012)

A Method for Measuring of RTN by Boosting Word-Line Voltage in 6-Tr-SRAMs. - Goichi Ono; Yuki Mori; Michiaki Nakayama; Yusuke Kanno (IEICE Trans. Electron., 2014)

Soft-Error-Tolerant Dual-Modular-Redundancy Architecture with Repair and Retry Scheme for Memory-Control Circuit on FPGA. - Makoto Saen; Tadanobu Toba; Yusuke Kanno (IEICE Trans. Electron., 2017)

Design Method for Online Totally Self-Checking Comparators Implementable on FPGAs. - Yusuke Kanno; Tadanobu Toba; Kotaro Shimamura; Nobuyasu Kanekawa (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A cryogenic pulse shaper for spin qubit control utilizing 1ns-time-resolution ADCs on an active silicon interposer operating at sub-100 mK temperatures. - Ryozo Takahashi; Yusuke Kanno; Takuji Miki; Nobuhiro Kusuno; Hiroyuki Mizuno; Makoto Nagata (A-SSCC, 2024)

Home Care Services in the Last Year of Life by Type of Care Management. - Sakiko Itoh; Tomomi Sakano; Mieko Sagawa; Rie Yanagiya; Yusuke Kanno; Kayo Hirooka; Sakiko Fukui (Nursing Informatics, 2024)