A Hardware Maze Router with Application to Interactive Rip-Up and Reroute. - Kei Suzuki; Yusuke Matsunaga; Masayoshi Tachibana; Tatsuo Ohtsuki (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986)

co-LODEX: A Cooperative Expert System for Logic design. - Fumihiro Maruyama; Taeko Kakuda; Yusuke Matsunaga; Yoriko Minoda; Shuho Sawada; Nobuaki Kawato (FGCS, 1988)

Multi-level logic optimization using binary decision diagrams. - Yusuke Matsunaga; Masahiro Fujita (ICCAD, 1989)

Boolean Resubstitution with Permissible Functions and Binary Decision Diagrams. - Hitomi Sato; Yoshihiro Yasue; Yusuke Matsunaga; Masahiro Fujita (DAC, 1990)

Automatic and Semi-Automatic Verification of Switch-Level Circuits with Temporal Logic and Binary Decision Diagrams. - Masahiro Fujita; Yusuke Matsunaga; Takeo Kakuda (ICCAD, 1990)

Multi-Level Logic Minimization Across Latch Boundaries. - Yusuke Matsunaga; Masahiro Fujita; Takeo Kakuda (ICCAD, 1990)

Boolean technology mapping for both ECI and CMOS circuits based on permissible functions and binary decision diagrams. - Hitomi Sato; Norikazu Takahashi; Yusuke Matsunaga; Masahiro Fujita (ICCD, 1990)

A Resynthesis Approach for Network Optimization. - Kuang-Chien Chen; Yusuke Matsunaga; Saburo Muroga; Masahiro Fujita (DAC, 1991)

On variable ordering of binary decision diagrams for the application of multi-level logic synthesis. - Masahiro Fujita; Yusuke Matsunaga; Taeko Kakuda (EURO-DAC, 1991)

Multi-Level Logic Minimization Based on Minimal Support and its Application to the Minimization of Look-Up Table Type FPGAs. - Masahiro Fujita; Yusuke Matsunaga (ICCAD, 1991)

On Computing the Transitive Closure of a State Transition Relation. - Yusuke Matsunaga; Patrick C. McGeer; Robert K. Brayton (DAC, 1993)

Variable ordering algorithms for ordered binary decision diagrams and their evaluation. - Masahiro Fujita; Hisanori Fujisawa; Yusuke Matsunaga (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

LP based cell selection with constraints of timing, area, and power consumption. - Yutaka Tamiya; Yusuke Matsunaga; Masahiro Fujita (ICCAD, 1994)

Implicit prime compatible generation for minimizing incompletely specified finite state machines. - Hiroyuki Higuchi; Yusuke Matsunaga (ASP-DAC, 1995)

A New Algorithm for Boolean Matching Utilizing Structural Information. - Yusuke Matsunaga (IEICE Trans. Inf. Syst., 1995)

A Fast State Reduction Algorithm for Incompletely Specified Finite State Machines. - Hiroyuki Higuchi; Yusuke Matsunaga (DAC, 1996)

An Efficient Equivalence Checker for Combinational Circuits. - Yusuke Matsunaga (DAC, 1996)

On accelerating pattern matching for technology mapping. - Yusuke Matsunaga (ICCAD, 1998)

The statistical longest path problem and its application to delay analysis of logical circuits. - Ei Ando; Masafumi Yamashita; Toshio Nakata; Yusuke Matsunaga (Timing Issues in the Specification and Synthesis of Digital Systems, 2002)

An Efficient Algorithm Finding Simple Disjoint Decompositions Using BDDs. - Yusuke Matsunaga (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Enhancing the performance of multi-cycle path analysis in an industrial setting. - Hiroyuki Higuchi; Yusuke Matsunaga (ASP-DAC, 2004)

Practical Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints. - Makoto Sugihara; Kazuaki J. Murakami; Yusuke Matsunaga (ISVLSI, 2004)

Cell Library Development Methodology for Throughput Enhancement of Electron Beam Direct-Write Lithography Systems. - Makoto Sugihara; Taiga Takata; Kenta Nakamura; Ryoichi Inanami; Hiroaki Hayashi; Katsumi Kishimoto; Tetsuya Hasebe; Yukihiro Kawano; Yusuke Matsunaga; Kazuaki J. Murakami; Katsuya Okumura (SoC, 2005)

Development of practical ATPG tool with flexible interface. - Masayoshi Yoshimura; Yusuke Matsunaga (ATS, 2006)

A character size optimization technique for throughput enhancement of character projection lithography. - Makoto Sugihara; Taiga Takata; Kenta Nakamura; Ryoichi Inanami; Hiroaki Hayashi; Katsumi Kishimoto; Tetsuya Hasebe; Yukihiro Kawano; Yusuke Matsunaga; Kazuaki J. Murakami; Katsuya Okumura (ISCAS, 2006)

Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment. - Makoto Sugihara; Taiga Takata; Kenta Nakamura; Ryoichi Inanami; Hiroaki Hayashi; Katsumi Kishimoto; Tetsuya Hasebe; Yukihiro Kawano; Yusuke Matsunaga; Kazuaki J. Murakami; Katsuya Okumura (IEICE Trans. Electron., 2006)

Area minimization algorithm for parallel prefix adders under bitwise delay constraints. - Taeko Matsunaga; Yusuke Matsunaga (ACM Great Lakes Symposium on VLSI, 2007)

Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa. - Yusuke Matsunaga (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Special Section on VLSI Design and CAD Algorithms. - Yusuke Matsunaga (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders. - Taeko Matsunaga; Yusuke Matsunaga (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

A Simultaneous Module Selection, Scheduling, and Allocation Method Considering Operation Chaining with Multi-Functional Units. - Tsuyoshi Sadakata; Yusuke Matsunaga (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Technology Mapping Technique for Increasing Throughput of Character Projection Lithography. - Makoto Sugihara; Kenta Nakamura; Yusuke Matsunaga; Kazuaki J. Murakami (IEICE Trans. Electron., 2007)

An efficient performance improvement method utilizing specialized functional units in Behavioral Synthesis. - Tsuyoshi Sadakata; Yusuke Matsunaga (ASP-DAC, 2008)

Area recovery under depth constraint by Cut Substitution for technology mapping for LUT-based FPGAs. - Taiga Takata; Yusuke Matsunaga (ASP-DAC, 2008)

Synthesis of parallel prefix adders considering switching activities. - Taeko Matsunaga; Shinji Kimura; Yusuke Matsunaga (ICCD, 2008)

A Behavioral Synthesis Method with Special Functional Units. - Tsuyoshi Sadakata; Yusuke Matsunaga (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Character Projection Mask Set Optimization for Enhancing Throughput of MCC Projection Systems. - Makoto Sugihara; Yusuke Matsunaga; Kazuaki J. Murakami (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs. - Taiga Takata; Yusuke Matsunaga (ACM Great Lakes Symposium on VLSI, 2009)

Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs. - Taiga Takata; Yusuke Matsunaga (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Binding Refinement for Multiplexer Reduction. - Sho Kodama; Yusuke Matsunaga (IPSJ Trans. Syst. LSI Des. Methodol., 2009)

Framework for Parallel Prefix Adder Synthesis Considering Switching Activities. - Taeko Matsunaga; Shinji Kimura; Yusuke Matsunaga (IPSJ Trans. Syst. LSI Des. Methodol., 2009)

Area Recovery under Depth Constraint for Technology Mapping for LUT-based FPGAs. - Taiga Takata; Yusuke Matsunaga (IPSJ Trans. Syst. LSI Des. Methodol., 2009)

Multi-operand adder synthesis on FPGAs using generalized parallel counters. - Taeko Matsunaga; Shinji Kimura; Yusuke Matsunaga (ASP-DAC, 2010)

A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only). - Taiga Takata; Yusuke Matsunaga (FPGA, 2010)

A Soft Error Tolerance Estimation Method for Sequential Circuits. - Masayoshi Yoshimura; Yusuke Akamine; Yusuke Matsunaga (DFT, 2011)

Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. - Shusuke Yoshimoto; Takuro Amashita; D. Kozuwa; Taiga Takata; Masayoshi Yoshimura; Yusuke Matsunaga; Hiroto Yasuura; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IOLTS, 2011)

Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs. - Taeko Matsunaga; Shinji Kimura; Yusuke Matsunaga (ISLPED, 2011)

Multi-Operand Adder Synthesis Targeting FPGAs. - Taeko Matsunaga; Shinji Kimura; Yusuke Matsunaga (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Neutron-induced soft error rate estimation for SRAM using PHITS. - Shusuke Yoshimoto; Takuro Amashita; Masayoshi Yoshimura; Yusuke Matsunaga; Hiroto Yasuura; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IOLTS, 2012)

A Robust Algorithm for Pessimistic Analysis of Logic Masking Effects in Combinational Circuits. - Taiga Takata; Yusuke Matsunaga (IPSJ Trans. Syst. LSI Des. Methodol., 2012)

An Exact Estimation Algorithm of Error Propagation Probability for Sequential Circuits. - Masayoshi Yoshimura; Yusuke Akamine; Yusuke Matsunaga (IPSJ Trans. Syst. LSI Des. Methodol., 2012)

An Exact Approach for GPC-Based Compressor Tree Synthesis. - Taeko Matsunaga; Shinji Kimura; Yusuke Matsunaga (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Efficient Fault Simulation Algorithms for Analyzing Soft Error Propagation in Sequential Circuits. - Taiga Takata; Masayoshi Yoshimura; Yusuke Matsunaga (IPSJ Trans. Syst. LSI Des. Methodol., 2013)

Synthesis algorithm of parallel index generation units. - Yusuke Matsunaga (DATE, 2014)

Synthesis Algorithm for Parallel Index Generator. - Yusuke Matsunaga (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Accelerating SAT-Based Boolean Matching for Heterogeneous FPGAs Using One-Hot Encoding and CEGAR Technique. - Yusuke Matsunaga (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

A Test Pattern Compaction Method Using SAT-Based Fault Grouping. - Yusuke Matsunaga (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

An Accelerating Technique for SAT-based ATPG. - Yusuke Matsunaga (IPSJ Trans. Syst. LSI Des. Methodol., 2017)

An Efficient SAT-Attack Algorithm Against Logic Encryption. - Yusuke Matsunaga; Masayoshi Yoshimura (IOLTS, 2019)