Body bias grain size exploration for a coarse grained reconfigurable accelerator. - Yusuke Matsushita 001; Hayate Okuhara; Koichiro Masuyama; Yu Fujita; Ryuta Kawano; Hideharu Amano (FPL, 2016)

Vertical Packet Switching Elevator Network Using Inductive Coupling ThruChip Interface. - Akio Nomura; Hiroki Matsutani; Tadahiro Kuroda; Junichiro Kadomoto; Yusuke Matsushita 001; Hideharu Amano (CANDAR, 2016)

Multi-objective Optimization for Application Mapping and Body Bias Control on a CGRA. - Nguyen Anh Vu Doan; Yusuke Matsushita 001; Naoki Ando; Hayate Okuhara; Hideharu Amano (MCSoC, 2017)

Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accelerator. - Yusuke Matsushita 001; Hayate Okuhara; Koichiro Masuyama; Yu Fujita; Ryuta Kawano; Hideharu Amano (IEICE Trans. Inf. Syst., 2017)

Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface. - Akio Nomura; Yusuke Matsushita 001; Junichiro Kadomoto; Hiroki Matsutani; Tadahiro Kuroda; Hideharu Amano (Int. J. Netw. Comput., 2018)

Demonstration of Low Power Stream Processing Using a Variable Pipelined CGRA. - Takuya Kojima; Naoki Ando; Yusuke Matsushita 001; Hideharu Amano (FPL, 2019)