Yusuke Matsushita

According to our database, Yusuke Matsushita authored at least 6 papers between 2016 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2019

Demonstration of Low Power Stream Processing Using a Variable Pipelined CGRA.

Takuya Kojima, Naoki Ando, Yusuke Matsushita, Hideharu Amano

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

2018

Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface.

Akio Nomura, Yusuke Matsushita, Junichiro Kadomoto, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano

Int. J. Netw. Comput., 2018

2017

Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accelerator.

Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano

IEICE Trans. Inf. Syst., 2017

Multi-objective Optimization for Application Mapping and Body Bias Control on a CGRA.

Nguyen Anh Vu Doan, Yusuke Matsushita, Naoki Ando, Hayate Okuhara, Hideharu Amano

Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017

2016

Vertical Packet Switching Elevator Network Using Inductive Coupling ThruChip Interface.

Akio Nomura, Hiroki Matsutani, Tadahiro Kuroda, Junichiro Kadomoto, Yusuke Matsushita, Hideharu Amano

Proceedings of the Fourth International Symposium on Computing and Networking, 2016

Body bias grain size exploration for a coarse grained reconfigurable accelerator.

Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016