A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm2 cell in 32nm high-k metal-gate CMOS. - Yuki Fujimura; Osamu Hirabayashi; Takahiko Sasaki; Azuma Suzuki; Atsushi Kawasumi; Yasuhisa Takeyama; Keiichi Kushida; Gou Fukano; Akira Katayama; Yusuke Niki; Tomoaki Yabe (ISSCC, 2010)

A trimless, 0.5V-1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access. - Keiichi Kushida; Osamu Hirabayashi; Fumihiko Tachibana; Hiroyuki Hara; Atsushi Kawasumi; Azuma Suzuki; Yasuhisa Takeyama; Yuki Fujimura; Yusuke Niki; Miyako Shizuno; Shinichi Sasaki; Tomoaki Yabe (A-SSCC, 2011)

A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers. - Yusuke Niki; Atsushi Kawasumi; Azuma Suzuki; Yasuhisa Takeyama; Osamu Hirabayashi; Keiichi Kushida; Fumihiko Tachibana; Yuki Fujimura; Tomoaki Yabe (IEEE J. Solid State Circuits, 2011)

Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction. - Atsushi Kawasumi; Yasuhisa Takeyama; Osamu Hirabayashi; Keiichi Kushida; Fumihiko Tachibana; Yusuke Niki; Shinichi Sasaki; Tomoaki Yabe (ICICDT, 2012)

A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs. - Atsushi Kawasumi; Yasuhisa Takeyama; Osamu Hirabayashi; Keiichi Kushida; Fumihiko Tachibana; Yusuke Niki; Shinichi Sasaki; Tomoaki Yabe (VLSIC, 2012)

A supply-noise-rejection technique in ADPLL with noise-cancelling current source. - Yusuke Niki; Daisuke Miyashita; Hiroyuki Kobayashi; Shouhei Kousai (ESSCIRC, 2013)

A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit. - Fumihiko Tachibana; Osamu Hirabayashi; Yasuhisa Takeyama; Miyako Shizuno; Atsushi Kawasumi; Keiichi Kushida; Azuma Suzuki; Yusuke Niki; Shinichi Sasaki; Tomoaki Yabe; Yasuo Unekawa (IEEE J. Solid State Circuits, 2014)