A 250-Mb/s, 700-mW, 32-highway*8-b S/P converter LSI with cross-access memory. - Yusuke Ohtomo; Masao Suzuki (IEEE J. Solid State Circuits, 1992)

BiCMOS circuit technology for a 704 MHz ATM switch LSI. - Yusuke Ohtomo; Sadayuki Yasuda; Minoru Togashi; Massyuki Ino; Yasuyuki Tanabe; Jun-ichi Inoue; Masafumi Nogawa; Sshigeki Hino (IEEE J. Solid State Circuits, 1994)

A data-transition look-ahead DFF circuit for statistical reduction in power consumption. - Masafumi Nogawa; Yusuke Ohtomo (IEEE J. Solid State Circuits, 1998)

A 10-Gb/s (1.25 Gb/s×8)4×2 0.25-μm CMOS/SIMOX ATM switch based on scalable distributed arbitration. - Eiji Oki; Naoaki Yamanaka; Yusuke Ohtomo; Kazuhiko Okazaki; Ryusuke Kawano (IEEE J. Solid State Circuits, 1999)

A 10Gb/s burst-mode adaptive gain select limiting amplifier in 0.13µm CMOS. - Masafumi Nogawa; Yusuke Ohtomo; Shunji Kimura; Kazuyoshi Nishimura; Tomoaki Kawamura; Minoru Togashi (ISSCC, 2006)

A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13-$muhbox m$CMOS. - Yusuke Ohtomo; Kazuyoshi Nishimura; Masafumi Nogawa (IEEE J. Solid State Circuits, 2006)

SE3 Last Mile Access Options: PON/DSL/Cable/Wireless. - Larry DeVito; Yusuke Ohtomo (ISSCC, 2007)

High sensitivity APD burst-mode receiver for 10Gbit/s TDM-PON system. - Takashi Nakanishi; Ken-Ichi Suzuki; Youichi Fukada; Naoto Yoshimoto; Makoto Nakamura; Kazutoshi Kato; Kazuyoshi Nishimura; Yusuke Ohtomo; Makoto Tsubokawa (IEICE Electron. Express, 2007)

A 1ps-Resolution 2ns-Span 10Gb/s Data-Timing Generator with Spectrum Conversion. - Tomoaki Kawamura; Yusuke Ohtomo; Kazuyoshi Nishimura; Noboru Ishihara (ISSCC, 2008)

A 10.3125Gb/s Burst-Mode CDR Circuit using a δσ DAC. - Jun Terada; Kazuyoshi Nishimura; Shunji Kimura; Hiroaki Katsurai; Naoto Yoshimoto; Yusuke Ohtomo (ISSCC, 2008)

A wide range, over 9.6ns, skew compensation LSI for a flexible optical access system. - Yoshihito Sakai; Hideaki Kimura 002; Yusuke Ohtomo; Makoto Tsubokawa (IEICE Electron. Express, 2008)

A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOI. - Yusuke Ohtomo; Hiroshi Koizumi; Kazuyoshi Nishimura; Masafumi Nogawa (IEICE Trans. Electron., 2008)

A 10-Gb/s Burst-Mode Clock-and-Data Recovery IC with Frequency-Adjusting Dual Gated VCOs. - Yusuke Ohtomo; Masafumi Nogawa; Kazuyoshi Nishimura; Shunji Kimura; Tomoaki Yoshida; Tomoaki Kawamura; Minoru Togashi; Kiyomi Kumozaki (IEICE Trans. Electron., 2008)

A 10.3 Gb/s Burst-Mode CDR Using a ΔΣ DAC. - Jun Terada; Kazuyoshi Nishimura; Shunji Kimura; Hiroaki Katsurai; Naoto Yoshimoto; Yusuke Ohtomo (IEEE J. Solid State Circuits, 2008)

Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit. - Jun Terada; Yusuke Ohtomo; Kazuyoshi Nishimura; Hiroaki Katsurai; Shunji Kimura; Naoto Yoshimoto (ISSCC, 2009)

A 16Gbps laser-diode driver with interwoven peaking inductors in 0.18-µm CMOS. - Takeshi Kuboki; Yusuke Ohtomo; Akira Tsuchiya; Keiji Kishine; Hidetoshi Onodera (CICC, 2010)

Bandwidth enhancement for high speed amplifier utilizing mutually coupled on-chip inductors. - Akira Tsuchiya; Takeshi Kuboki; Yusuke Ohtomo; Keiji Kishine; Shigekazu Miyawaki; Makoto Nakamura; Hidetoshi Onodera (ISOCC, 2011)

An Injection-Controlled 10-Gb/s Burst-Mode CDR Circuit for a 1G/10G PON System. - Hiroaki Katsurai; Hideki Kamitsuna; Hiroshi Koizumi; Jun Terada; Yusuke Ohtomo; Tsugumichi Shibata (IEICE Trans. Electron., 2011)

A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18µm CMOS. - Takeshi Kuboki; Yusuke Ohtomo; Akira Tsuchiya; Keiji Kishine; Hidetoshi Onodera (ASP-DAC, 2012)

A 10Gb/s burst-mode laser diode driver for burst-by-burst power saving. - Hiroshi Koizumi; Minoru Togashi; Masafumi Nogawa; Yusuke Ohtomo (ISSCC, 2012)

Design method for an over-IO-Gb/s CMOS CML buffer circuit for delay control. - Keiji Kishine; Hiromi Inaba; Yusuke Ohtomo; Makoto Nakamura; Mitsuo Nakamura (MWSCAS, 2012)

Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System. - Takeshi Kuboki; Yusuke Ohtomo; Akira Tsuchiya; Keiji Kishine; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

A 25-Gb/s LD driver with area-effective inductor in a 0.18-µm CMOS. - Takeshi Kuboki; Yusuke Ohtomo; Akira Tsuchiya; Keiji Kishine; Hidetoshi Onodera (ASP-DAC, 2013)

Analysis and design based on small-signal equivalent circuit for a lO-GHz ring VCO with 65-nm CMOS. - Keiji Kishine; Hiromi Inaba; Yusuke Ohtomo; Makoto Nakamura; Hiroshi Koizumi; Mitsuo Nakamura (MWSCAS, 2013)

Small and Low-Cost Dual-Rate Optical Triplexer for OLT Transceivers in 10G/1G Co-existing 10G-EPON Systems. - Atsushi Kanda; Akira Ohki; Takeshi Kurosaki; Hiroaki Sanjoh; Kota Asaka; Ryoko Yoshimura; Toshio Ito; Makoto Nakamura; Masafumi Nogawa; Yusuke Ohtomo; Mikio Yoneyama (IEICE Trans. Electron., 2013)

An STM-16 Frame Termination VLSI With 2.5-Gb/s/Pin Input/Output Buffers: High-Speed and Low-Power Multi-𝕍DD CMOS/SIMOX Techniques. - Nobutaro Shibata; Yusuke Ohtomo; Mika Nishisaka; Yasuhiro Sato (IEEE Trans. Very Large Scale Integr. Syst., 2015)