At the Extreme of 3D-NAND Scaling: 25 nm Z-Pitch with 10 nm Word Line Cells. - S. Rachidi; Antonio Arreghini; Devin Verreck; G. L. Donadio; K. Banerjee; K. Katcko; Yusuke Oniki; Geert Van den Bosch; Maarten Rosmeulen (IMW, 2022)

First demonstration of Two Metal Level Semi-damascene Interconnects with Fully Self-aligned Vias at 18MP. - Gayle Murdoch; Matin O'Toole; Giulio Marti; Ankit Pokhrel; Diana Tsvetanova; Stefan Decoster; Shreya Kundu; Yusuke Oniki; Arame Thiam; Quoc Toan Le; Olalla Varela Pedreira; Alicja Lesniewska; et al. (VLSI Technology and Circuits, 2022)

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails. - Anabela Veloso; Anne Jourdain; D. Radisic; Rongmei Chen; G. Arutchelvan; B. O'Sullivan; Hiroaki Arimura; Michele Stucchi; An De Keersgieter; M. Hosseini; T. Hopf; K. D'Have; et al. (VLSI Technology and Circuits, 2022)

Molybdenum Nitride as a Scalable and Thermally Stable pWFM for CFET. - Hiroaki Arimura; S. Brus; Jacopo Franco; Yusuke Oniki; A. Vandooren; T. Conard; B. T. Chan; B. Kannan; M. Samiee; W. Li; P. Deminskyi; E. Shero; et al. (VLSI Technology and Circuits, 2023)

Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning. - Hans Mertens; M. Hosseini; Thomas Chiarella; D. Zhou; S. Wang; G. Mannaert; E. Dupuy; D. Radisic; Z. Tao; Yusuke Oniki; Andriy Hikavyy; R. Rosseel; et al. (VLSI Technology and Circuits, 2023)

Integration of a Stacked Contact MOL for Monolithic CFET. - Victor Vega-Gonzalez; D. Radisic; Bt Chan; S. Choudhury; S. Wang; A. Mingardi; Q. Toan Le; H. Decoster; Yusuke Oniki; P. Puttarame; Kevin Vandersmissen; J. P. Soulie; et al. (VLSI Technology and Circuits, 2023)